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MB9B160L Series
32-Bit Arm Cortex -M4F
FM4 Microcontroller
Devices in the MB9B160L Series are highly integrated 32-bit microcontrollers with high performance and competitive cost.
This series is based on the Arm Cortex -M4F Processor with on-chip Flash memory and SRAM. The series has peripheral
2
functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I C, LIN).
The products that are described in this datasheet are placed into TYPE2-M4 product categories in theFM4 Family Peripheral
Manual Main Part (002-04856).
Features
32-bit Arm Cortex -M4F Core [SRAM]
This is composed of three independent SRAMs (SRAM0,
Processor version: r0p1
SRAM1, and SRAM2). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
Up to 160 MHz Frequency Operation
connected to System bus of Cortex-M4F core.
FPU built-in
SRAM0: Up to 32 Kbytes
Support DSP instruction
SRAM1: Up to 16 Kbytes
Memory Protection Unit (MPU): improves the reliability of an
SRAM2: Up to 16 Kbytes
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
Multi-Function Serial Interface (Max 6 Channels)
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
64 bytes with FIFO (the FIFO step numbers are variable
depending on the settings of the communication mode or bit
24-bit System timer (Sys Tick): System timer for OS task
length.)
management
Operation mode is selectable from the followings for each
On-Chip Memories
channel.
UART
CSIO
[Flash Memory]
LIN
These series are based on two independent on-chip Flash
2
memories. I C
MainFlash memory UART
Up to 512 Kbytes Full-duplex double buffer
Built-in Flash Accelerator System with 16 Kbytes trace Selection with or without parity supported
buffer memory
Built-in dedicated baud rate generator
The read access to Flash memory can be achieved without
External clock available as a serial clock
wait-cycle up to operation frequency of 72 MHz. Even at
Hardware Flow control : Automatically control the
the operation frequency more than 72 MHz, an equivalent
transmission by CTS/RTS (only ch.4)
access to Flash memory can be obtained by Flash
Various error detect functions available (parity errors,
Accelerator System.
framing errors, and overrun errors)
Security function for code protection
CSIO
WorkFlash memory
Full-duplex double buffer
32 Kbytes
Built-in dedicated baud rate generator
Read cycle:
Overrun error detect function available
6wait-cycle: the operation frequency more than 120 MHz,
Serial chip select function (ch.6 only)
and up to 160 MHz
Supports high-speed SPI (ch.0 and ch.6 only)
4wait-cycle: the operation frequency more than 72 MHz,
Data length 5 to 16-bit
and up to 120 MHz
LIN
2wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz LIN protocol Rev.2.1 supported
Full-duplex double buffer
0wait-cycle: the operation frequency up to 40 MHz
Master/Slave mode supported
Security function is shared with code protection
LIN break field generation (can change to 13 to 16-bit
length)
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 002-04976 Rev.*B Revised December 15, 2017