MB9BF216S/T MB9BF217S/T, MB9BF218S/T 32-bit ARM Cortex -M3 based FM3 Microcontroller The MB9B210T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I2C, LIN, Ethernet-MAC). The products which are described in this data sheet are placed into TYPE2 product categories inFM3 Family PERIPHERAL MANUA. Features Supports Address/Data multiplex 32-bit ARM Cortex-M3 Core Supports external RDY input Processor version: r2p1 USB Interface (Max 2channels) Up to 144 MHz Frequency Operation USB interface is composed of Function and Host. Memory Protection Unit (MPU): improves the reliability of an PLL for USB is built-in, USB clock or Ethernet clock can be embedded system generated by multiplication of Main clock. Integrated Nested Vectored Interrupt Controller (NVIC): 1 USB function NMI (non-maskable interrupt) and 48 peripheral interrupts USB2.0 Full-Speed supported and 16 priority levels Max 6 EndPoint supported 24-bit System timer (Sys Tick): System timer for OS task management EndPoint 0 is control transfer EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer On-chip Memories EndPoint 3-5 can be selected Bulk-transfer or Flash memory Interrupt-transfer Up to 1 Mbyte EndPoint 1 to 5 is comprised Double Buffer EndPoint 0, 2 to 5:64 bytes Built-in Flash Accelerator System with 16 Kbyte trace buffer EndPoint 1: 256 bytes memory The read access to Flash memory can be achieved without USB host wait cycle up to operation frequency of USB2.0 Full/Low speed supported 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Bulk-transfer, interrupt-transfer and Isochronous-transfer Flash Accelerator System. support Security function for code protection USB Device connected/dis-connected automatically detect SRAM IN/OUT token handshake packet automatically This Series contain a total of up to 128 Kbyte on-chip SRAM. Max 256-byte packet-length supported This is composed of two independent SRAM (SRAM0, SRAM1) . SRAM0 is connected to I-code bus and D-code Wake-up function supported bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 64 Kbyte. Ethernet - MAC (Max 1 channel) SRAM1: Up to 64 Kbyte. Compliant with IEEE802.3 specification 10Mbps / 100 Mbps data transfer rates supported External Bus Interface MII/RMII for external PHY device supported. Supports SRAM, NOR and NAND Flash device MII: Max 1channel RMII: Max 1channel Up to 8 chip selects Full-Duplex and Half-Duplex mode supported. 8-/16-bit Data width Wake-ON-LAN supported Up to 25-bit Address bit Built-in dedicated descriptor-system DMAC Maximum area size : Up to 256 Mbytes Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04680 Rev.*A Revised April 5, 2016 MB9B210T Series Built-in 2 Kbyte Transmit FIFO and 2 Kbyte Receive FIFO. Number of transfers: 1 to 65536 Compliant IEEE1558-2008 (PTP) A/D Converter (Max 32 channels) 12-bit A/D Converter Multi-function Serial Interface (Max 8 channels) Successive Approximation Register type 4 channels with 16steps9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3) Built-in 3 unit Operation mode is selectable from the followings for each Conversion time: 1.0 s 5 V channel. Priority conversion available (priority at 2 levels) UART CSIO Scanning conversion mode LIN Built-in FIFO for conversion data storage (for SCAN 2 I C conversion: 16 steps, for Priority conversion: UART 4 steps) Full-duplex double buffer Base Timer (Max 16 channels) Selection with or without parity supported Operation mode is selectable from the followings for each Built-in dedicated baud rate generator channel. External clock available as a serial clock 16-bit PWM timer Hardware Flow control : Automatically control the 16-bit PPG timer transmission by CTS/RTS (only ch.4) 16-/32-bit reload timer Various error detect functions available (parity errors, framing 16-/32-bit PWC timer errors, and overrun errors) CSIO General Purpose I/O Port Full-duplex double buffer This series can use its pins as General Purpose I/O ports when they are not used for external bus or peripherals. Moreover, the Built-in dedicated baud rate generator port relocate function is built in. It can set which I/O port the Overrun error detect function available peripheral function can be allocated. LIN Capable of pull-up control per pin LIN protocol Rev.2.1 supported Capable of reading pin level directly Full-duplex double buffer Built-in the port relocate function Master/Slave mode supported Up 154 fast General Purpose I/O Ports 176 pin Package LIN break field generate (can be changed 13-16-bit length) Some pin is 5 V tolerant I/O. LIN break delimiter generate (can be changed 1-4-bit length) SeePin Descriptio to confirm the corresponding pins Various error detect functions available (parity errors, framing Multi-function Timer (Max 3 units) errors, and overrun errors) 2 I C The Multi-function timer is composed of the following blocks. Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) 16-bit free-run timer 3ch./unit supported Input capture 4ch./unit DMA Controller (8 channels) Output compare 6ch./unit DMA Controller has an independent bus for CPU, so CPU and A/D activation compare 3ch./unit DMA Controller can process simultaneously. Waveform generator 3ch./unit 8 independently configured and operated channels 16-bit PPG timer 3ch./unit Transfer can be started by software or request from the The following function can be used to achieve the motor built-in peripherals control. Transfer address area: 32 bit (4 Gbyte) PWM signal output function Transfer mode: Block transfer/Burst transfer/Demand DC chopper waveform output function transfer Dead time function Transfer data type: byte/half-word/word Input capture function Transfer block count: 1 to 16 Document Number: 002-04680 Rev.*A Page 2 of 141