S25FS064S 64 Mbit (8 Mbyte), 1.8 V FS-S Flash Features Serial Peripheral Interface (SPI) with Multi-I/O 20 Year Data Retention, minimum Security Features SPI Clock polarity and phase modes 0 and 3 Double Data Rate (DDR) option One Time Program (OTP) array of 1024 bytes Extended Addressing: 24- or 32-bit address options Block Protection: Serial Command subset and footprint compatible with S25- Status Register bits to control protection against program FL1-K, S25FL-P and S25FL-S SPI families or erase of a contiguous range of sectors. Multi I/O Command subset and footprint compatible with Hardware and software control options S25FL1-K S25FL-P and S25FL-S SPI families Advanced Sector Protection (ASP) Read Individual sector protection controlled by boot code or Commands: Normal, Fast, Dual Output, Dual I/O, Quad Out- password put, Quad I/O, DDR Quad I/O Option for password control of read access Modes: Burst Wrap, Continuous (XIP), QPI (QPI) Technology Serial Flash Discoverable Parameters (SFDP) and Common Cypress 65 nm MirrorBit Technology with Eclipse Archi- Flash Interface (CFI), for configuration information. tecture Program Single Supply Voltage with CMOS I/O 256 or 512 Bytes Page Programming buffer 1.7 V to 2.0 V Program suspend and resume Temperature Range Automatic ECC -internal hardware Error Correction Code generation with single bit error correction Industrial ( 40 C to +85 C) Erase Industrial Plus ( 40 C to +105 C) Extended (40 C to +125 C) Hybrid sector option Automotive, AEC-Q100 Grade 3 (40 C to +85 C) Physical set of eight 4KB sectors and one 32KB sector at the top or bottom of address space with all remaining sec- Automotive, AEC-Q100 Grade 2 (40 C to +105 C) tors of 64KB Automotive, AEC-Q100 Grade 1 (40 C to +125 C) Uniform sector option Packages (all Pb-free) Uniform 64KB or 256KB blocks for software compatibility 8-lead SOIC 208 mil (SOC008) with higher density and future devices LGA 5x6 mm (W9A008) Erase suspend and resume BGA-24 6 8 mm Erase status evaluation 5 5 ball (FAB024) footprint Cycling Endurance 100,000 Program-Erase Cycles, minimum Data Retention Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-03631 Rev. *F Revised April 06, 2018S25FS064S Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 SO/IO1 Y Decoders I/O Data Latch WP /IO2 Control Logic RESET /IO3 Data Path RESET Document Number: 002-03631 Rev. *F Page 2 of 146 X Decoders