Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS29GL064S 64-Mbit (8 Mbyte), 3.0 V, Flash Memory Distinctive Characteristics CMOS 3.0 Volt Core with Versatile I/O Package Options 48-pin TSOP Architectural Advantages 56-pin TSOP Single Power Supply Operation 64-ball Fortified BGA (LAA064 13 mm 11 mm 1.4 mm) (LAE064 9 mm 9 mm 1.4 mm) Manufactured on 65 nm MirrorBit Process Technology 48-ball fine-pitch BGA (VBK048 8.15 mm 6.15 mm Secure Silicon Region 1.0 mm) 128-word/256-byte sector for permanent, secure Temperature Range identification through an 8-word / 16-byte random Electronic Serial Number, accessible through a command Industrial ( 40C to +85C) sequence Industrial Plus ( 40C to +105C) Programmed and locked at the factory or by the customer Automotive, AEC-Q100 Grade 3 ( 40C to +85C) Flexible Sector Architecture Automotive, AEC-Q100 Grade 2( 40C to +105C) 64 Mb (uniform sector models): One hundred twenty-eight Software and Hardware Features 32-kword (64-kB) sectors 64 Mb (boot sector models): One hundred twenty-seven Software Features 32-kword (64-kB) sectors + eight 4kword (8kB) boot Advanced Sector Protection: offers Persistent Sector sectors Protection and Password Sector Protection Automatic Error Checking and Correction (ECC) - internal Program Suspend and Resume: read other sectors before hardware ECC with single bit error correction programming operation is completed Erase Suspend and Resume: read / program other sectors Enhanced VersatileI/O Control before an erase operation is completed All input levels (address, control, and DQ input levels) and Data polling and toggle bits provide status outputs are determined by voltage on V input. V range IO IO is 1.65 to V CFI (Common Flash Interface) compliant: allows host CC system to identify and accommodate multiple flash devices Compatibility with JEDEC Standards Unlock Bypass Program command reduces overall Provides pinout and software compatibility for single-power multiple-word programming time supply flash, and superior inadvertent write protection Hardware Features 100,000 Erase Cycles per Sector Minimum WP /ACC input supports manufacturing programming 20-year Data Retention Typical operations (when high voltage is applied). Protects first or last sector regardless of sector protection settings on Performance Characteristics uniform sector models High Performance Hardware reset input (RESET ) resets device 70 ns access time Ready/Busy output (RY/BY ) detects program or erase 8-word / 16-byte page read buffer cycle completion 15 ns page read time 128-word / 256-byte write buffer which reduces overall programming time for multiple-word updates Low Power Consumption 25 mA typical initial read current 5 MHz 7.5 mA typical page read current 33 MHz 50 mA typical erase / program current 40 A typical standby mode current Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98286 Rev. *H Revised August 03, 2018