S70FL256P0XMFI000 Infineon

S70FL256P 256-Mbit 3.0V Flash This product is not recommended for new and current designs. For new and current designs, the S25FL256S supersedes S70FL256P. This is the factory-recommended migration path. Refer to the S25FL256S datasheet for specifications and ordering information, and AN98592 for changes required to migrate from existing designs based on S70FL256P. Distinctive Characteristics One-time programmable (OTP) area on each Flash die for Architectural Advantages permanent, secure identification can be programmed and Single Power Supply Operation locked at the factory or by the customer Full voltage range: 2.7 to 3.6V read and write operations CFI (Common Flash Interface) compliant: allows host Memory Architecture system to identify and accommodate multiple flash devices Uniform 64 kB sectors Process Technology Top or bottom parameter block (Two 64-kB sectors Manufactured on 0.09 m MirrorBit process technology broken down into sixteen 4-kB sub-sectors each) for each Flash die Package Option Uniform 256 kB sectors (no 4-kB sub-sectors) Industry Standard Pinouts 256-byte page size 16-pin SO package (300 mils) 24-ball BGA (6 8 mm) package, 5 5 pin configuration Program Page Program (up to 256 bytes) in 1.5 ms (typical) Performance Characteristics Program operations are on a page by page basis Accelerated programming mode via 9V W /ACC pin Speed Quad Page Programming Normal READ (Serial): 40 MHz clock rate FAST READ (Serial): 104 MHz clock rate (maximum) Erase DUAL I/O FAST READ: 80 MHz clock rate or Bulk erase function for each Flash die 20 MB/s effective data rate Sector erase (SE) command (D8h) for 64 kB and 256 kB QUAD I/O FAST READ: 80 MHz clock rate or sectors 40 MB/s effective data rate Sub-sector erase (P4E) command (20h) for 4 kB sectors (for uniform 64-kB sector device only) Power Saving Standby Mode Sub-sector erase (P8E) command (40h) for 8 kB sectors Standby Mode 160 A (typical) (for uniform 64-kB sector device only) Deep Power-Down Mode 6 A (typical) Cycling Endurance Memory Protection Features 100,000 cycles per sector typical Memory Protection Data Retention W /ACC pin works in conjunction with Status Register Bits 20 years typical to protect specified memory areas Device ID Status Register Block Protection bits (BP2, BP1, BP0) in JEDEC standard two-byte electronic signature status register configure parts of memory as read-only RES command one-byte electronic signature for backward compatibility Software Features SPI Bus Compatible Serial Interface General Description This document contains information for the S70FL256P device, which is a dual die stack of two S25FL129P die. For detailed specifications, refer to the discrete die datasheet. Document Name Cypress Document Number S25FL129P, 128-Mbit 3.0V Flash Memory Datasheet 002-00648 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00647 Rev. *F Revised March 10, 2016 Not Recommended for New DesignS70FL256P Contents 1. Block Diagram.............................................................. 3 7. DC Characteristics........................................................ 7 2. Connection Diagrams.................................................. 4 8. Test Conditions............................................................. 8 3. Input/Output Description............................................. 5 9. AC Characteristics........................................................ 9 9.1 Capacitance.................................................................. 10 4. Logic Symbol ............................................................... 5 10. Ordering Information.................................................. 11 5. Device Operations ....................................................... 6 10.1 Valid Combinations....................................................... 11 5.1 Programming ................................................................. 6 5.2 Simultaneous Die Operation.......................................... 6 11. Physical Dimensions.................................................. 12 5.3 Sequential Reads........................................................... 6 11.1 SL3 016 16-pin Wide Plastic Small 5.4 Sector/Bulk Erase .......................................................... 6 Outline Package (300-mil Body Width) .........................12 5.5 Status Register .............................................................. 6 11.2 ZSA024 24-ball Ball Grid Array (6 8 mm) 5.6 Configuration Register ................................................... 6 Package ........................................................................13 5.7 Block Protection............................................................. 6 12. Revision History.......................................................... 14 6. Read Identification (RDID)........................................... 6 Document Number: 002-00647 Rev. *F Page 2 of 16 Not Recommended for New Design