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Stratix V Device Overview 2015.10.01 Send Feedback SV51001 Subscribe Alteras 28-nm Stratix V FPGAs include innovations such as an enhanced core architecture, integrated transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual property (IP) blocks. With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices optimized for: Bandwidth-centric applications and protocols, including PCI Express (PCIe ) Gen3 Data-intensive applications for 40G/100G and beyond High-performance, high-precision digital signal processing (DSP) applications Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low- risk, low-cost path to HardCopy V ASICs. Related Information Stratix V Device Handbook: Known Issues Lists the planned updates to the Stratix V Device Handbook chapters. Stratix V Family Variants The Stratix V device family contains the GT, GX, GS, and E variants. Stratix V GT devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are optimized for applications that require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communica tions systems and optical test systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and GX channels, respectively. Stratix V GX devices offer up to 66 integrated transceivers with 14.1-Gbps data rate capability. These transceivers also support backplane and optical interface applications. These devices are optimized for high-performance, high-bandwidth applications such as 40G/100G optical transport, packet processing, and traffic management found in wireline, military communications, and network test equipment markets. Stratix V GS devices have an abundance of variable precision DSP blocks, supporting up to 3,926 18x18 or 1,963 27x27 multipliers. In addition, Stratix V GS devices offer integrated transceivers with 14.1-Gbps data rate capability. These transceivers also support backplane and optical interface applications. These devices are optimized for transceiver-based DSP-centric applications found in wireline, military, broadcast, and high-performance computing markets. 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as ISO trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance 9001:2008 of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any Registered products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134SV51001 2 Stratix V Features Summary 2015.10.01 Stratix V E devices offer the highest logic density within the Stratix V family with nearly one million logic elements (LEs) in the largest device. These devices are optimized for applications such as ASIC and system emulation, diagnostic imaging, and instrumentation. Common to all Stratix V family variants are a rich set of high-performance building blocks, including a redesigned adaptive logic module (ALM), 20 Kbit (M20K) embedded memory blocks, variable precision DSP blocks, and fractional phase-locked loops (PLLs). All of these building blocks are interconnected by Alteras superior multi-track routing architecture and comprehensive fabric clocking network. Also common to Stratix V devices is the new Embedded HardCopy Block, which is a customizable hard IP block that leverages Alteras unique HardCopy ASIC capabilities. The Embedded HardCopy Block in Stratix V FPGAs is used to harden IP instantiation of PCIe Gen3, Gen2, and Gen1. Stratix V Features Summary Table 1: Summary of Features for Stratix V Devices Feature Description Technology 28-nm TSMC process technology 0.85-V or 0.9-V core voltage Low-power serial 28.05-Gbps transceivers on Stratix V GT devices transceivers Electronic dispersion compensation (EDC) for XFP, SFP+, QSFP, CFP optical module support Adaptive linear and decision feedback equalization Transmitter pre-emphasis and de-emphasis Dynamic reconfiguration of individual channels On-chip instrumentation (EyeQ non-intrusive data eye monitoring) Backplane capability 600-Megabits per second (Mbps) to 12.5-Gbps data rate capability General-purpose I/Os 1.6-Gbps LVDS (GPIOs) 1,066-MHz external memory interface On-chip termination (OCT) 1.2-V to 3.3-V interfacing for all Stratix V devices Embedded HardCopy PCIe Gen3, Gen2, and Gen1 complete protocol stack, x1/x2/x4/x8 end Block point and root port Embedded transceiver Interlaken physical coding sublayer (PCS) hard IP Gigabit Ethernet (GbE) and XAUI PCS 10G Ethernet PCS Serial RapidIO (SRIO) PCS Common Public Radio Interface (CPRI) PCS Gigabit Passive Optical Networking (GPON) PCS Power management Programmable Power Technology Quartus II integrated PowerPlay Power Analysis Stratix V Device Overview Altera Corporation Send Feedback