IS41C16256C IS41LV16256C 256Kx16 4Mb DRAM WITH EDO PAGE MODE JANUARY 2013 DESCRIPTION FEATURES The IS41C16256C and IS41LV16256C are 262,144 x 16-bit TTL compatible inputs and outputs tr i-state I/O high-perfor mance CMOS Dynamic Random Access Memo- Refresh Inter val: 512 cycles/8 ms r ies. Both products offer accelerated cycle access EDO Refresh Mode : RAS-Only, CAS-before-RAS (CBR), Page Mode. EDO Page Mode allows 512 random accesses and Hidden within a single row with access cycle time as shor t as 14ns JEDEC standard pinout per 16-bit word. It is asynchronous, as it does not require a clock signal input to synchronize commands and I/O. Single power supply: 5V 10% (IS41C16256C) These features make the IS41C/LV16256C ideally suited for 3.3V 10% (IS41LV16256C) high band-width graphics, digital signal processing, high- performance computing systems, and peripheral applications Byte Wr ite and Byte Read operation via two CAS that r un without a clock to synchronize with the DRAM. Industr ial Temperature Range -40C to +85C The IS41C/LV16256C is packaged in 40-pin TSOP (Type II). KEY TIMING PARAMETERS Parameter -35 Unit Max. RAS Access Time (tcra ) 35 ns Max. CAS Access Time (tcca) 13 ns Max. Column Address Access Time (taa ) 18 ns Min. EDO Page Mode Cycle Time (tpc ) 14 ns Min. Read/Wr ite Cycle Time (trc ) 60 ns Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. A 1/31/2013IS41C16256C IS41LV16256C PIN CONFIGURATIONS 40-Pin TSOP (Type II) VDD 1 40 GND I/O0 2 39 I/O15 I/O1 3 38 I/O14 I/O2 4 37 I/O13 I/O3 5 36 I/O12 VDD 6 35 GND I/O4 7 34 I/O11 I/O5 8 33 I/O10 32 I/O6 9 I/O9 31 I/O7 10 I/O8 NC 11 30 NC NC 12 29 LCAS WE 13 28 UCAS RAS 14 27 OE NC 15 26 A8 A0 16 25 A7 A1 17 24 A6 A2 18 23 A5 A3 19 22 A4 VDD 20 21 GND PIN DESCRIPTIONS A0-A8 Address Inputs I/O0-15 Data Inputs/Outputs WE Wr ite Enable OE Output Enable RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vdd Power GND Ground NC No Connection 2 Integrated Silicon Solution, Inc. Rev. A 1/31/2013