Product Information


IS42S16100H-7TL-TR electronic component of ISSI

DRAM 16M 3.3V SDRAM 1Mx16 143MhzRoHS

Manufacturer: ISSI
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges

Price (USD)

1: USD 2.191 ea
Line Total: USD 2.191

397 - Global Stock
Ships to you between
Thu. 12 Oct to Mon. 16 Oct
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
378 - Global Stock

Ships to you between Thu. 12 Oct to Mon. 16 Oct

MOQ : 1
Multiples : 1
1 : USD 1.539
10 : USD 1.365
100 : USD 1.165
500 : USD 1.1076
1000 : USD 1.062
2000 : USD 1.0512
5000 : USD 1.0272
10000 : USD 1.0044
25000 : USD 0.9756

Product Category
Mounting Style
Package / Case
TSOP - 50
Data Bus Width
16 bit
1 M x 16
Memory Size
16 Mbit
Maximum Clock Frequency
143 MHz
Access Time
6 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
Supply Current - Max
50 mA
Minimum Operating Temperature
0 C
Maximum Operating Temperature
+ 70 C
Cut Tape , Reel
Hts Code
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IS42S16100H IS45S16100H 512K Words x 16 Bits x 2 Banks OCTOBER 2016 16Mb SYNCHRONOUS DYNAMIC RAM FEATURES DESCRIPTION Clock frequency: 200, 166, 143 MHz ISSI s 16Mb Synchronous DRAM IS42/4516100H Fully synchronous all signals referenced to a is organized as a 524,288-word x 16-bit x 2-bank for positive clock edge improved perfor mance. The synchronous DRAMs achieve high-speed data transfer using pipeline Two banks can be operated simultaneously and architecture. All inputs and outputs signals refer to the independently rising edge of the clock input. Dual inter nal bank controlled by A11 (bank select) Single 3.3V power supply LVTTL interface Programmable burst length (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave 2048 refresh cycles ever y 32ms (Com, Ind, A1 grade) or 16ms (A2 grade) Random column address ever y clock cycle Programmable CAS latency (2, 3 clocks) Burst read/wr ite and burst read/single wr ite operations capability Burst ter mination by burst stop and precharge command Byte controlled by LDQM and UDQM Packages: 400-mil 50-pin TSOP-II and 60-ball TF-BGA Temperature Grades: o o Commercial (0 C to +70 C) o o Industr ial (-40 C to +85 C) o o Automotive A1 (-40 C to +85 C) o o Automotive A2 (-40 C to +105 C) Copyright 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can rea- sonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica- tions unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. A1 10/11/2016IS42S16100H, IS45S16100H PIN CONFIGURATIONS 50-Pin TSOP (Type II) VDD 1 50 GND DQ0 2 49 DQ15 DQ1 3 48 DQ14 GNDQ 4 47 GNDQ DQ2 5 46 DQ13 DQ3 6 45 DQ12 VDDQ 7 44 VDDQ DQ4 8 43 DQ11 DQ5 9 42 DQ10 GNDQ 10 41 GNDQ DQ6 11 40 DQ9 39 DQ7 12 DQ8 VDDQ 13 38 VDDQ LDQM 14 37 NC WE 15 36 UDQM CAS 16 35 CLK RAS 17 34 CKE CS 18 33 NC A11 19 32 A9 A10 20 31 A8 30 A0 21 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VDD 25 26 GND PIN DESCRIPTIONS A0-A10 Row Address Input CAS Column Address Strobe Command A11 Bank Select Address WE Wr ite Enable A0-A7 Column Address Input LDQM Lower Bye, Input/Output Mask DQ0 to DQ15 Data DQ UDQM Upper Bye, Input/Output Mask CLK System Clock Input VDD Power CKE Clock Enable GND Ground CS Chip Select VDDQ Power Supply for DQ Pin RAS Row Address Strobe Command GNDQ Ground for DQ Pin NC No Connection 2 Integrated Silicon Solution, Inc. Rev. A1 10/11/2016

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:
Integrated Silicon Solution
Integrated Silicon Solution ()
Integrated Silicon Solution (ISSI)
ISSI(Integrated Silicon Solution)
ISSI, Integrated Silicon Solution Inc