Product Information


Product Image X-ON

DRAM Chip DDR SDRAM 128Mbit 8Mx16 2.5V 66-Pin TSOP-II T/R

Manufacturer: ISSI
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges

Price (USD)

1: USD 0.7467 ea
Line Total: USD 0.7467

1142 - Global Stock
Ships to you between
Tue. 13 Jun to Mon. 19 Jun
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
1142 - Global Stock

Ships to you between Tue. 13 Jun to Mon. 19 Jun

MOQ : 1
Multiples : 1
1 : USD 0.7467
10 : USD 0.7349
25 : USD 0.7227
100 : USD 0.7108
250 : USD 0.6965
500 : USD 0.6965
1000 : USD 0.6965

Product Category
Mounting Style
Package / Case
TSOP - 66
Data Bus Width
16 bit
8 M x 16
Memory Size
128 Mbit
Maximum Clock Frequency
200 MHz
Access Time
5 ns
Supply Voltage - Max
2.7 V
Supply Voltage - Min
2.3 V
Supply Current - Max
240 mA
Minimum Operating Temperature
0 C
Maximum Operating Temperature
+ 70 C
Show Stocked Products With Similar Attributes. LoadingGif
Image Description
Stock Image IS43R16800E-6TLI
Memory; SDRAM; 8Mx16bit; 166MHz; 6ns; TSOP66 II; -40÷85°C; 2.5VDC
Stock : 39
Stock Image IS43R32400E-4BL
ISSI DRAM 128M (4Mx32) 250MHz 2.5v DDR SDRAM
Stock : 0
Stock Image IS43R32400E-5BL
DRAM 128M, 2.5V, DDR, 4Mx32, 200MHz @ CL3, 144-ball BGA (12mmx12mm) RoHS
Stock : 24
Stock Image IS43R32400E-5BLI
DRAM 128M, 2.5V, DDR, 4Mx32, 200MHz @ CL3, 144-ball BGA (12mmx12mm) RoHS, IT
Stock : 0
Stock Image IS43R32800D-6BL
DRAM 256M, 2.5V, DDR, 8Mx32, 166MHz, 144-ball BGA (12mmx12mm) RoHS
Stock : 0
Stock Image IS43R32400D-4BL
DRAM Chip DDR SDRAM 128Mbit 4Mx32 2.5V 144-Pin LFBGA
Stock : 0
Stock Image IS43R83200D-6TL
DRAM 256M, 2.5V, DDR, 32Mx8, 166MHz, 66 pin TSOP II (400 mil) RoHS
Stock : 0
Stock Image IS43R16800E-6TL
ISSI DRAM 128M (8Mx16) 166MHz 2.5v DDR SDRAM
Stock : 90
Stock Image IS43R32800D-5BLI
ISSI DRAM 256M (16Mx16) 200MHz 2.5v DDR SDRAM
Stock : 0
Stock Image IS43R32800D-5BL
ISSI DRAM 256M (16Mx16) 200MHz 2.5v DDR SDRAM
Stock : 5
Image Description
Stock Image IS43R16320D-5TLI

ISSI DRAM 512M (32Mx16) 200MHz 2.5v DDR SDRAM
Stock : 18

Stock Image IS43R16320D-5BLI

ISSI DRAM 512M (32Mx16) 200MHz 2.5v DDR SDRAM
Stock : 0

Stock Image IS43R16160F-5TL

ISSI DRAM 256M, 2.5V, DDR, 16Mx16, 166MHz
Stock : 120

Stock Image IS43R16160D-6TL-TR

DRAM Chip DDR SDRAM 256Mbit 16Mx16 2.5V 66-Pin TSOP-II T/R
Stock : 0

Stock Image IS43R16160D-5BLI

ISSI DRAM 256M (16Mx16) 200MHz 2.5v DDR SDRAM
Stock : 95

Stock Image IS43LR16320C-6BLI

DRAM Chip Mobile-DDR SDRAM 512Mbit 32Mx16 1.8V 60-Pin TFBGA
Stock : 232

Stock Image IS43DR81280B-25DBLI

ISSI DRAM 1G (128Mx8) 400MHz 1.8v DDR2 SDRAM
Stock : 254

Stock Image IS43DR16640C-3DBL

DRAM DDR2,1G,1.8V, RoHs 333MHz,64Mx16
Stock : 1929

Stock Image IS43DR16320C-3DBLI-TR

DRAM 512M, 1.8V, DDR2, 32Mx16, 333Mhz @ CL5, 84 ball BGA (8mmx12.5mm) RoHS, IT, T&R
Stock : 1000

Stock Image IS43DR16128C-3DBL

DRAM DDR2,2G,1.8V, RoHs 333MHz,128Mx16
Stock : 108

IS43/46R16800E, IS43/46R32400E 4Mx32, 8Mx16 JANUARY 2014 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW VDD and VDDQ: 2.5V 0.2V (-5,-6) ISSIs 128-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word VDD and VDDQ: 2.5V 0.1V (-4) accesses per clock cycle. The 134,217,728-bit memor y SSTL 2 compatible I/O array is inter nally organized as four banks of 32Mb to Double-data rate architecture two data transfers allow concurrent operations. The pipeline allows Read per clock cycle and Write burst accesses to be virtually continuous, with Bidirectional, data strobe (DQS) is transmitted/ the option to concatenate or tr uncate the bursts. The received with data, to be used in capturing data programmable features of burst length, burst sequence at the receiver and CAS latency enable fur ther advantages. The device DQS is edge-aligned with data for READs and is available in 16-bit and 32-bit data word size Input centre-aligned with data for WRITEs data is registered on the I/O pins on both edges of Differential clock inputs (CK and CK) Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. DLL aligns DQ and DQS transitions with CK Commands are registered on the positive edges of CLK. transitions Commands entered on each positive CK edge data An Auto Refresh mode is provided, along with a Self and data mask referenced to both edges of DQS Refresh mode. All I/Os are SSTL 2 compatible. Four inter nal banks for concurrent operation ADDRESS TABLE Data Mask for wr ite data. DM masks wr ite data Parameter 4M x 32 8M x 16 at both rising and falling edges of data strobe Configuration 1M x 32 x 4 2M x 16 x 4 Burst Length: 2, 4 and 8 banks banks Burst Type: Sequential and Inter leave mode Bank Address BA0, BA1 BA0, BA1 Programmable CAS latency: 2, 2.5, 3, and 4 Pins Auto Refresh and Self Refresh Modes Autoprecharge A8/AP A10/AP Auto Precharge Pins Tras Lockout suppor ted (trap = trcd ) Row Address 4K(A0 A11) 4K(A0 A11) Column 256(A0 A7) 512(A0 A8) OPTIONS Address Configuration(s): 4Mx32, 8Mx16 Refresh Count Package(s): Com./Ind./A1 4K / 64ms 4K / 64ms 144 Ball BGA (x32) A2 4K / 16ms 4K / 16ms 66-pin TSOP-II (x16) and 60 Ball BGA (x16) Lead-free package available KEY TIMING PARAMETERS Temperature Range: S p e e d Gr ad e -4 -5 -6 Units Commercial (0C to +70C) Fck M a x C L = 4 25 0 MHz Industr ial (-40C to +85C) Fck M a x C L = 3 200 200 167 MHz Automotive, A1 (-40C to +85C) Fck M a x C L = 2 . 5 167 167 MHz Automotive, A2 (-40C to +105C) Fck M a x C L = 2 133 133 MHz Copyright 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. C 1/16/14IS43/46R16800E, IS43/46R32400E FUNCTIONAL BLOCK DIAGRAM (x 32) CK COMMAND CK DM0-DM3 DECODER DATA IN 4 CKE & BUFFER CS CLOCK 32 RAS 32 GENERATOR I/O 0-31 CAS REFRESH DQS0-DQS3 WE CONTROLLER Mode Registers and 4 Ext. Mode Registers SELF VDD/VDDQ DATA OUT REFRESH Vss/VssQ BUFFER CONTROLLER 14 32 32 A11 A10 A9 A8 REFRESH A7 COUNTER 2 A6 A5 4096 A4 12 4096 MEMORY CELL A3 4096 ARRAY A2 4096 12 A1 BANK 0 ROW A0 ROW ADDRESS BA0 ADDRESS LATCH 12 BUFFER BA1 12 12 SENSE AMP I/O GATE 2 256 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 8 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 8 2 Integrated Silicon Solution, Inc. Rev. C 1/16/14 MULTIPLEXER ROW DECODER

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:
Integrated Silicon Solution
Integrated Silicon Solution ()
Integrated Silicon Solution (ISSI)
ISSI(Integrated Silicon Solution)
ISSI, Integrated Silicon Solution Inc