IS46LD32640B-18BLA2-TR

IS43/46LD16128B IS43/46LD32640B 2Gb (x16, x32) Mobile LpddR2 s 4 sdRAM FeBRUARY 2018 FeAt URes descR iption The IS43/46LD16128B/32640B is 2Gbit CMOS Low-voltage Core and I/O Power Supplies LPDDR2 DRAM. The device is organized as 8 banks VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, of 16Meg words of 16bits or 8Meg words of 32bits. VDD1 = 1.70-1.95V This product uses a double-data-rate architecture to High Speed Un-terminated Logic(HSUL 12) I/O achieve high-speed operation. The double data rate Interface architecture is essentially a 4N prefetch architecture Clock Frequency Range : 10MHz to 533MHz with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully (data rate range : 20Mbps to 1066Mbps per I/O) synchronous operations referenced to both rising and Four-bit Pre-fetch DDR Architecture falling edges of the clock. The data paths are internally Multiplexed, double data rate, command/ad- pipelined and 4n bits prefetched to achieve very high dress inputs bandwidth. Eight internal banks for concurrent operation Bidirectional/differential data strobe per byte of data (DQS/DQS ) Programmable Read/Write latencies(RL/WL) Add Ress t ABLe and burst lengths(4,8 or 16) Parameter 64Mx32 128Mx16 ZQ Calibration Row Addresses R0-R13 R0-R13 On-chip temperature sensor to control self re- Column Addresses C0-C8 C0-C9 fresh rate Bank Addresses BA0-BA2 BA0-BA2 Partial array self refresh(PASR) Refresh Count 8192 8192 Deep power-down mode(DPD) Operation Temperature Commercial (TC = 0C to 85C) (1) k eY ti MinG pARAMete Rs Industrial (TC = -40C to 85C) Automotive, A1 (TC = -40C to 85C) Speed Data Write Read tRCD/ (2) Automotive, A2 (TC = -40C to 105C) Grade Rate Latency Latency tRP (3) Automotive, A25 (TC = -40C to 115C) (Mb/s) -18 1066 4 8 Typical options -25 800 3 6 Typical Configuration: -3 667 2 5 Typical 128Mx16 (16M x 16 x 8 banks) 64Mx32 (8M x 32 x 8 banks) Notes: Package: 1. Other clock frequencies/data rates supported please refer to AC timing tables. 134-ball BGA for x16 / x32 2. Please contact ISSI for Fast trcd /trp . 168-ball PoP BGA for x32 3. When Tc > 105C, Self-Refresh mode is not supported Copyright 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A 02/02/2018IS43/46LD16128B IS43/46LD32640B BALL Assi GnMents And desc Riptions 134-ball FBGA (x32), 0.65mm pitch 1 2 3 4 5 6 7 8 9 10 DNU DNU DNU DNU A A DNU NC NC VDD2 VDD1 DQ31 DQ29 DQ26 DNU B B VDD1 VSS RFU VSS VSSQ VDDQ DQ25 VSSQ VDDQ C C VSS VDD2 ZQ VDDQ DQ30 DQ27 DQS3 DQS3 VSSQ D D DQ VSSCA CA9 CA8 DQ28 DQ24 DM3 DQ15 VDDQ VSSQ E E CA VDDCA CA6 CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ F F Power VDD2 CA5 Vref(CA) DQS1 DQS1 DQ10 DQ9 DQ8 VSSQ G G Ground VDDCA VSS CK DM1 VDDQ H H No ball VSSCA NC CK VSSQ VDDQ VDD2 VSS Vref(DQ) J J ZQ CKE RFU RFU DM0 VDDQ K K Clock CS RFU RFU DQS0 DQS0 DQ5 DQ6 DQ7 VSSQ L L NC, DNU, RFU CA4 CA3 CA2 VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ M M VSSCA VDDCA CA1 DQ19 DQ23 DM2 DQ0 VDDQ VSSQ N N VSS VDD2 CA0 VDDQ DQ17 DQ20 DQS2 DQS2 VSSQ P P VDD1 VSS NC VSS VSSQ VDDQ DQ22 VSSQ VDDQ R R DNU NC NC VDD2 VDD1 DQ16 DQ18 DQ21 DNU T T DNU DNU DNU DNU U U 1 2 3 4 5 6 7 8 9 10 Top View (ball down) 2 Integrated Silicon Solution, Inc. www.issi.com Rev. A 02/02/2018