IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 1Mx18, 512Kx36 OCTOBER 2014 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES DESCRIPTION The 18Mb IS61DDPB251236A/A1/A2 and 512Kx36 and 1Mx18 configuration available. IS61DDPB21M18A/A1/A2 are synchronous, high- On-chip Delay-Locked Loop (DLL) for wide data performance CMOS static random access memory (SRAM) valid window. devices. These SRAMs have a common I/O bus. The rising Common I/O read and write ports. edge of K clock initiates the read/write operation, and all Synchronous pipeline read with self-timed late write internal operations are self-timed. Refer to the Timing operation. Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Double Data Rate (DDR) interface for read and write input ports. Read and write addresses are registered on alternating rising 2.5 cycle read latency. edges of the K clock. Reads and writes are performed in Fixed 2-bit burst for read and write operations. double data rate. Clock stop support. The following are registered internally on the rising edge of Two input clocks (K and K ) for address and control the K clock: registering at rising edges only. Read/write address Two echo clocks (CQ and CQ ) that are delivered Read enable simultaneously with data. Write enable +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. Byte writes HSTL input and output interface. Data-in for first burst addresses Registered addresses, write and read controls, byte Data-Out for second burst addresses writes, data in, and data outputs. The following are registered on the rising edge of the K Full data coherency. clock: Byte writes Boundary scan using limited set of JTAG 1149.1 functions. Data-in for second burst addresses Byte write capability. Data-Out for first burst addresses Fine ball grid array (FBGA) package: Byte writes can change with the corresponding data-in to 13mm x 15mm & 15mm x 17mm body size enable or disable writes on a per-byte basis. An internal write 165-ball (11 x 15) array buffer enables the data-ins to be registered one cycle after Programmable impedance output drivers via 5x the write address. The first data-in burst is clocked one cycle user-supplied precision resistor. later than the write command signal, and the second burst is Data Valid Pin (QVLD). timed to the following rising edge of the K clock. ODT (On Die Termination) feature is supported optionally on data input, K/K , and BW . During the burst read operation, the data-outs from the first x bursts are updated from output registers of the third rising The end of top mark (A/A1/A2) is to define options. edge of the K clock (starting two and half cycles later after IS61DDPB251236A : Dont care ODT function read command). The data-outs from the second burst are and pin connection updated with the fourth rising edge of the K clock where read IS61DDPB251236A1 : Option1 command receives at the first rising edge of K. IS61DDPB251236A2 : Option2 The device is operated with a single +1.8V power supply and Refer to more detail description at page 6 for each is compatible with HSTL I/O interfaces. ODT option. Copyright 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. A 10/02/2014 IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 Package ballout and description x36 FBGA Ball Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 1 1 1 CQ NC/SA NC/SA R/W BW K BW LD SA NC/SA CQ 2 1 A NC DQ27 DQ18 SA BW K BW SA NC NC DQ8 3 0 B NC NC DQ28 V SA SA SA V NC DQ17 DQ7 SS 0 SS C NC DQ29 DQ19 V V V VSS V NC NC DQ16 SS SS SS SS D NC NC DQ20 V V V VSS V NC DQ15 DQ6 DDQ SS SS DDQ E NC DQ30 DQ21 V V V V V NC NC DQ5 DDQ DD SS DD DDQ F NC DQ31 DQ22 V V V V V NC NC DQ14 DDQ DD SS DD DDQ G D V V V V V V V V V ZQ off REF DDQ DDQ DD SS DD DDQ DDQ REF H NC NC DQ32 V V V V V NC DQ13 DQ4 DDQ DD SS DD DDQ J NC NC DQ23 V V V V V NC DQ12 DQ3 DDQ DD SS DD DDQ K NC DQ33 DQ24 V V V V V NC NC DQ2 DDQ SS SS SS DDQ L NC NC DQ34 V V V V V NC DQ11 DQ1 SS SS SS SS SS M NC DQ35 DQ25 V SA SA SA V NC NC DQ10 SS SS N P NC NC DQ26 SA SA C SA SA NC DQ9 DQ0 TDO TCK SA SA SA C SA SA SA TMS TDI R Notes: 1. The following balls are reserved for higher densities: 3A for 36M, 10A for 72Mb and 2A for 144Mb. x18 FBGA Ball Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 1 1 1 CQ NC/SA SA R/W BW K NC/SA LD SA NC/SA CQ A 1 1 NC DQ9 NC SA NC/SA K BW SA NC NC DQ8 0 B NC NC NC V SA SA SA V NC DQ7 NC C SS 0 SS NC NC DQ10 V V V VSS V NC NC NC D SS SS SS SS NC NC DQ11 V V V VSS V NC NC DQ6 E DDQ SS SS DDQ NC DQ12 NC V V V V V NC NC DQ5 F DDQ DD SS DD DDQ NC NC DQ13 V V V V V NC NC NC DDQ DD SS DD DDQ G D V V V V V V V V V ZQ H off REF DDQ DDQ DD SS DD DDQ DDQ REF NC NC NC V V V V V NC DQ4 NC J DDQ DD SS DD DDQ NC NC DQ14 V V V V V NC NC DQ3 K DDQ DD SS DD DDQ NC DQ15 NC V V V V V NC NC DQ2 L DDQ SS SS SS DDQ NC NC NC V V V V V NC DQ1 NC SS SS SS SS SS M NC NC DQ16 V SA SA SA V NC NC NC N SS SS P NC NC DQ17 SA SA C SA SA NC NC DQ0 TDO TCK SA SA SA C SA SA SA TMS TDI R Notes: 1. The following balls are reserved for higher densities: 10A for 36M, 2A for 72Mb, 7A for 144Mb, 5B for 288Mb. Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A 10/02/2014