Product Information

IS61LF51218B-7.5TQLI

IS61LF51218B-7.5TQLI electronic component of ISSI

Datasheet
SRAM SYNC.FLOW-THRU 7.5ns 512K x18 3.3v IO

Manufacturer: ISSI
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

72: USD 10.3219 ea
Line Total: USD 743.18

0 - Global Stock
MOQ: 72  Multiples: 72
Pack Size: 72
Availability Price Quantity
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Ships to you between Fri. 26 Apr to Thu. 02 May

MOQ : 72
Multiples : 1
72 : USD 15.3212

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Ships to you between Fri. 26 Apr to Thu. 02 May

MOQ : 72
Multiples : 72
72 : USD 13.1898

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Ships to you between Thu. 02 May to Mon. 06 May

MOQ : 72
Multiples : 72
72 : USD 12.558
288 : USD 12.4545
504 : USD 12.305
1008 : USD 12.144
2520 : USD 12.121
5040 : USD 11.9945

0 - Global Stock


Ships to you between Fri. 26 Apr to Thu. 02 May

MOQ : 72
Multiples : 72
72 : USD 10.3219

     
Manufacturer
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RoHS - XON
Icon ROHS
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Access Time
Maximum Clock Frequency
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Supply Voltage - Max
Supply Voltage - Min
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Moisture Sensitive
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IS61(64)LF25636B, IS61VF/VVF25636B IS61(64)LF51218B, IS61VF/VVF51218B 256K x 36, 512K x 18 MARCH 2020 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION FEATURES The 9Mb product family features high-speed, low-power Internal self-timed write cycle synchronous static RAMs designed to provide burstable, Individual Byte Write Control and Global Write high-performance memory for communication and network- ing applications. The IS61(64)LF/VF25636B is organized Clock controlled, registered address, data and as 262,144 words by 36 bits. The IS61(64)LF/VF51218B control is organized as 524,288 words by 18 bits. Fabricated with ISSI s advanced CMOS technology, the device integrates Burst sequence control using MODE input a 2-bit burst counter, high-speed SRAM core, and high- Three chip enable option for simple depth expan- drive capability outputs into a single monolithic circuit. All sion and address pipelining synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Common data inputs and data outputs Write cycles are internally self-timed and are initiated by the Auto Power-down during deselect rising edge of the clock input. Write cycles can be one to Single cycle deselect four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be writ- Snooze MODE for reduced-power standby ten. Byte write operation is performed by using byte write JTAG Boundary Scan for BGA package enable (BWE) input combined with one or more individual byte write signals (BWxIn ). addition, Global Write (GW) Power Supply is available for writing all bytes at one time, regardless of LF: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) the byte write controls. VF: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) VVF: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%) input pins. Subsequent burst addresses can be gener- ated internally and controlled by the ADV (burst address JEDEC 100-Pin QFP, 119-pin BGA, and 165-pin advance) input pin. BGA packages The mode pin is used to select the burst sequence order, Lead-free available Linear burst is achieved when this pin is tied LOW. Inter- leave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter -6.5 -7.5 Units tkq Clock Access Time 6.5 7.5 ns tkc Cycle Time 7.5 8.5 ns Frequency 133 117 MHz Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. B2 03/04/2020IS61(64)LF25636B, IS61VF/VVF25636B IS61(64)LF51218B, IS61VF/VVF51218B BLOCK DIAGRAM MODE A0 A0 CLK Q0 BINARY /CKE COUNTER A1 A1 Q1 /ADV /CE /ADSC /CLR /ADSP 256Kx36 512Kx18 D Q A0-x Memory Array x18: x=18 ADDRESS x36: x=17 REGISTER /CE CLK /GW D Q /BWE DQ(a-d) BYTE WRITE /BW(a-x) REGISTERS x18:x=b, INPUT x32,x36:x=d REGISTER CLK /CE D Q CE2 CLK ENABLE /CE2 OUTPUT REGISTERS DQ(a-x) REGISTER x18:x=b, Power x32,x36:x=d ZZ CLK Down CLK /OE 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. B2 03/04/2020

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
Integrated Silicon Solution
Integrated Silicon Solution ()
Integrated Silicon Solution (ISSI)
INTEGRATED SILICON SOLUTIONS INC
ISSI
ISSI(Integrated Silicon Solution)
ISSI, Integrated Silicon Solution Inc
Lumissil

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