IS62WV102416GALL/BLL IS65WV102416GALL/BLL FEBURARY 2020 1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns DESCRIPTION CMOS low power operation The ISSI IS62/65WV102416GALL/BLL are high-speed, low power, 16M bit static RAMs organized as 1024K words by Operating Current: 35mA (max.) 16 bits. It is fabricated using ISSI s high-performance CMOS CMOS standby Current: 5.5uA (typ.) technology. TTL compatible interface levels This highly reliable process coupled with innovative circuit Single power supply design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or 1.65V-2.2V VDD (IS62/65WV102416GALL) when CS2 is LOW (deselected) or when CS1 is LOW, 2.2V-3.6V VDD (IS62/65WV102416GBLL) CS2 is HIGH and both LB and UB are HIGH, the device Three state outputs assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Commercial, Industrial and Automotive Easy memory expansion is provided by using Chip Enable temperature support and Output Enable inputs. The active LOW Write Enable Lead-free available (WE ) controls both writing and reading of the memory. A data byte allows Upper Byte (UB ) and Lower Byte (LB ) access. FUNCTIONAL Block Diagram The device supports 16 I/Os when BYTE is High, and 8 I/Os when BYTE is Low. In x8 mode, UB , LB , and 1024K x 16 (2048Kx8) I/O8~I/O14 are not used, and I/O15 becomes A20. DECODER MEMORY A0 A19(20) ARRAY VDD The IS62/65WV102416GALL/BLL are packaged in the GND JEDEC standard 48-Pin TSOP (TYPE I) I/O0 I/O7 I/O Lower Byte . DATA COLUMN I/O I/O8 I/O15 CIRCUIT Upper Byte BYTE CS2 CS1 CONTROL OE CIRCUIT WE UB LB Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. A4 02/11/2020 IS62WV102416GALL/BLL IS65WV102416GALL/BLL PIN CONFIGURATIONS 48-Pin TSOP (TYPE I) PIN DESCRIPTIONS A0-A19 Address Inputs A16 A15 1 48 I/O0-I/O14 Data Inputs/Outputs BYTE A14 2 47 3 A13 VSS 46 I/O15/A20 I/O15, when used in a x16 mode, 4 I/O15/A20 A12 45 A20 when used in a x8 mode. 5 I/O7 A11 44 A10 I/O14 6 CS1 , CS2 Chip Enable Inputs 43 42 7 I/O6 A9 OE Output Enable Input I/O13 A8 8 41 I/O5 A19 9 40 WE Write Enable Input NC 39 I/O12 10 I/O4 LB Lower-byte Control WE 11 38 CS2 12 VDD 37 (I/O0-I/O7) NC 13 I/O11 36 UB Upper-byte Control I/O3 UB 14 35 LB 34 I/O10 (I/O8-I/O15) 15 I/O2 A18 16 33 BYTE Must be tied to VDD to use as X16 or A17 32 I/O9 17 VSS to use as X8. UB ,LB , I/O 8~I/O14 A7 31 I/O1 18 A6 30 I/O8 19 are not used and I/O 15 become A20 in 20 I/O0 A5 29 x8 mode. A4 21 OE 28 NC No Connection VSS A3 22 27 CS1 A2 23 26 VDD Power A1 24 25 A0 VSS Ground Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A4 02/11/2020