Product Information


IS62WV25616BLL-55TI electronic component of ISSI

SRAM Chip Async Single 3.3V 4M-bit 256K x 16 55ns 44-Pin TSOP-II

Manufacturer: ISSI
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges

Price (USD)

135: USD 6.2587 ea
Line Total: USD 844.9245

0 - Global Stock
MOQ: 135  Multiples: 135
Pack Size: 135
Availability Price Quantity
0 - Global Stock

Ships to you between Fri. 06 Oct to Thu. 12 Oct

MOQ : 135
Multiples : 135
135 : USD 6.2587

Product Category
Memory Size
4 mb it
256 K X 16
Access Time
55 ns
Interface Type
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
Package / Case
TSOP II - 44
Supply Current - Max
15 mA
Data Rate
Factory Pack Quantity :
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IS62WV25616ALL IS62WV25616BLL 256Kx16LO W VOLTAGE, JUNE2011 ULTRALOWPOWERCMOSSTATICSRAM FEATURES DESCRIPTION The ISSI IS62WV25616ALL/IS62WV25616BLL are high- High-speed access time: 55ns, 70ns speed, low power, 4M bit SRAMs organized as 256K words CMOS low power operation by 16 bits. It is fabricated using ISSI s high-performance 36 mW (typical) operating CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance 9 W (typical) CMOS standby and low power consumption devices. TTL compatible interface levels When CS1 is HIGH (deselected) or when CS1 is LOW and Single power supply both LB and UB are HIGH, the device assumes a standby 1.65V--2.2VV dd (IS62WV25616ALL) mode at which the power dissipation can be reduced down 2.5V--3.6VV dd (IS62WV25616BLL) with CMOS input levels. Fully static operation: no clock or refresh Easy memory expansion is provided by using Chip Enable required and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte Three state outputs allows Upper Byte (UB) and Lower Byte (LB) access. Data control for upper and lower bytes The IS62WV25616ALL/IS62WV25616BLL are packaged Industrial temperature available in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin Lead-free available mini BGA (6mmx8mm). FUNCTIONALBLOCK DIA GRAM 256K x 16 A0-A17 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CS1 OE CONTROL CIRCUIT WE UB LB Copyright 2011 Integrated Silicon Solution, Inc.All rights reserv ed.ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services descrCustomersibed herein. are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effProductsectiveness are. not authorized for use in such applications unless Integrated Silicon Solution, Inc.receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1-800-379-4774 1 Rev. E 06/03/2011IS62WV25616ALL, IS62WV25616BLL PINCONFIGURATIONS 44-Pinmini TSOP(T ypeII) 48-ballminiBGA(6mmx8mm) (PackageCode T) (PackageCodeB) A4 1 44 A5 1 2 3 4 5 6 A3 2 43 A6 A2 3 42 A7 41 A1 4 OE A0 5 40 UB CS1 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 A LB OE A0 A1 A2 NC I/O2 9 36 I/O13 I/O3 10 35 I/O12 I/O UB A3 A4 CSI I/O B 8 0 VDD 11 34 GND GND 12 33 VDD I/O I/O A5 A6 I/O I/O C 9 10 1 2 I/O4 13 32 I/O11 I/O5 14 31 I/O10 GND I/O A17 A7 I/O VDD 11 3 D I/O6 15 30 I/O9 VDD I/O NC A16 I/O GND I/O7 16 29 I/O8 E 12 4 WE 17 28 NC I/O I/O A14 A15 I/O I/O F 14 13 5 6 A16 18 27 A8 A15 19 26 A9 I/O NC A12 A13 WE I/O 15 7 G A14 20 25 A10 21 24 A13 A11 NC A8 A9 A10 A11 NC H A12 22 23 A17 PINDESCRIPTIONS A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1 Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground 2 1-800-379-4774 Integrated Silicon Solution, Inc. Rev. E 06/03/2011

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
Integrated Silicon Solution
Integrated Silicon Solution ()
Integrated Silicon Solution (ISSI)
ISSI(Integrated Silicon Solution)
ISSI, Integrated Silicon Solution Inc