Memory Module Speci cations KVR1333D3N9H/8G 8GB 2Rx8 1G x 64-Bit PC3-10600 CL9 240-Pin DIMM Important Information: The module defined in this data sheet is one of several configurations available under this part number. While all configurations are compatible, the DRAM combination and/or the module height may vary from what is described here. DESCRIPTION SPECIFICATIONS This document describes ValueRAM s 1G x 64-bit (8GB) CL(IDD) 9 cycles DDR3-1333 CL9 SDRAM (Synchronous DRAM), 2Rx8, memory Row Cycle Time (tRCmin) 49.5ns (min.) module, based on sixteen 512M x 8-bit FBGA components. The Refresh to Active/Refresh 260ns (min.) SPD is programmed to JEDEC standard latency DDR3-1333 Command Time (tRFCmin) timing of 9-9-9 at 1.5V. This 240-pin DIMM uses gold contact Row Active Time (tRASmin) 36ns (min.) fingers. The electrical and mechanical specifications are as Maximum Operating Power 2.460 W* follows: UL Rating 94 V - 0 o o Operating Temperature 0 C to 85 C o o Storage Temperature -55 C to +100 C FEATURES JEDEC standard 1.5V (1.425V ~1.575V) Power Supply *Power will vary depending on the SDRAM used. VDDQ = 1.5V (1.425V ~ 1.575V) 667MHz fCK for 1333Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 9, 8, 7, 6 Programmable Additive Latency: 0, CL - 2, or CL - 1 clock Programmable CAS Write Latency(CWL) = 7 (DDR3-1333) 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4 with tCCD = 4 which does not allow seamless read or write either on the fly using A12 or MRS Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) On Die Termination using ODT pin Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95C Asynchronous Reset PCB: Height 1.18 (30mm), double sided component Continued >> Document No. VALUERAM1037-001.B00 05/18/12 Page 1MODULE DIMENSIONS: Document No. VALUERAM1037-001.B00 Page 2