KVR13R9S4L/8

Memory Module Speci cations KVR13R9S4L/8 8GB 1Rx4 1G x 72-Bit PC3-10600 CL9 Registered w/Parity 240-Pin DIMM DESCRIPTION SPECIFICATIONS This document describes ValueRAM s 1G x 72-bit (8GB) CL(IDD) 9 cycles DDR3L-1333 CL9 SDRAM (Synchronous DRAM), registered w/ Row Cycle Time (tRCmin) 49.5ns (min.) parity, 1Rx4 ECC VLP memory module, based on eighteen 1G Refresh to Active/Refresh 260ns (min.) x 4-bit FBGA components. The SPD is programmed to JEDEC Command Time (tRFCmin) standard latency DDR3-1333 timing of 9-9-9 at 1.5V. This 240- Row Active Time (tRASmin) 36ns (min.) pin DIMM uses gold contact fingers. The electrical and me- Maximum Operating Power 5.601 W* chanical specifications are as follows: UL Rating 94 V - 0 o o Operating Temperature 0 C to 85 C o o Storage Temperature -55 C to +100 C FEATURES JEDEC standard 1.5V (1.425V ~1.575V) Power Supply *Power will vary depending on the SDRAM and Register/PLL used. VDDQ = 1.5V (1.425V ~ 1.575V) 667MHz fCK for 1333Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 9, 8, 7, 6 Programmable Additive Latency: 0, CL - 2, or CL - 1 clock Programmable CAS Write Latency(CWL) = 7 (DDR3-1333) 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4 with tCCD = 4 which does not allow seamless read or write either on the fly using A12 or MRS Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) On Die Termination using ODT pin On-DIMM thermal sensor (Grade B) Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95C Asynchronous Reset PCB : Height 0.740 (18.75mm), double sided component Continued >> Document No. VALUERAM1257-001.A00 09/24/12 Page 1MODULE DIMENSIONS: Document No. VALUERAM1257-001.A00 Page 2