f u l l y t e s t e d a n d i n t e r o p e r a b l e
Lattice Ethernet Solutions
Ready-to-Use Ethernet Portfolio
Lattice provides customers with low cost and low power program-
mable solutions that are ready-to-use right out of the box. A full
suite of tested and interoperable solutions is available for Ethernet
applications, including:
FPGAs with Embedded Ethernet-compliant SERDES
A Complete Portfolio of Soft and Hard IP Cores for 10GbE,
2.5GbE, 1GbE, and 10/100 Ethernet Stacks
Application Specific Development Boards, Systems and
Reference Designs
Test and Interoperability Reports for PMA, PCS and MACs
Silicon: Industry Leading Programmable Ethernet Platforms
LatticeECP3 Low Cost FPGA LatticeSC Extreme Performance FPGA
Embedded 3.2Gbps SERDES support
Quad SERDES + Embedded PCS each
PCI Express, Ethernet (XAUI, 1GbE,
channel runs from 600Mbps to 3.8Gbps
SERDES SERDESSERDESSERDES
SGMII), CPRI, OBSAI & 3G/HD/SD-SDI. with 105mW power dissipation.
SERDES SERDES SERDES SERDES
Programmable Function Unit (PFU)
Programmable Function Unit (PFU)
perform Logic, Arithmetic, Distributed
perform Logic, Arithmetic, Distributed
RAM and Distributed ROM functions.
RAM and Distributed ROM functions.
Pre-Engineered Source Synchronous
Programmable I/O Cells (PICs) include
Support implements DDR3 at
PURESPEED buffers that support
800Mbps, SPI4.2 at 750Mbps and
over 20 I/O standards.
generic interfaces up to 1Gbps.
Structured ASIC Block (MACO)
sysDSP Blocks implement multipliers,
provides 50,000 usable gates for
adders, subtractors, accumulators.
increased performance, density and
lower power.
sysMEM Embedded Block RAM (EBR)
provides 18kbit dual port RAM.
sysMEM Embedded Block RAM (EBR)
provides 18kbit dual port RAM.
sysCLOCK PLLs & DLLs for clock
management.
sysCLOCK PLLs & DLLs for clock
management.
LatticeECP3 Features
LatticeSC Features
Low Cost Digital SERDES High Performance Analog SERDES
Ideal for low cost chip-to-chip and small Exceeds XAUI TX and RX requirements
factor backplane applications Ideal for long Ethernet-based backplanes
Exceeds XAUI Tx and Rx requirements
Up to 32 Channels per Device
1000BaseX Jitter Compliant
Useful for multi-port switching
Up to 16 Channels per Device
Data Rates Up to 3.8 Gbps
Useful for multi-port switching
Exceeds XAUI baud rate specifications
Complete End-to-End Solution
Complete End-to-End Solution
Soft XAUI PCS and 10GbE MAC implementations available
Rich PCS functionality
Soft SGMII and TS-MAC implementations available
flexiMAC supports both GbE and 10GbE MACs, saves cost
Very Low SERDES Power (~110mW Per Channel Typical @ and power
3.2Gbps)
Soft SGMII and TS-MAC implementation available
Low Cost FPGA Fabric
Very Low SERDES Power (105mW Per Channel Typical @
High end features at low cost
3.125Gbps)
Extreme Performance FPGA Fabric
500MHz block level performanceIntellectual Property: Rich Portfolio of Hard & Soft IP
XAUI PCS GbE & SGMII PCS flexiPCS
Platform: Platform: Platform:
Soft IP Soft IP Hard PCS Block
Compliant to IEEE802.3ae for XAUI Compliant to IEEE802.3z Supports IEEE802.3ae TM
flexiPCS
Implements TX and RX State Machines MAC or PHY Modes (Pin Selectable) XAUI and IEEE GbE
XGMII Interface to FGPA Fabric RX and TX State Machines and PCS
Multiprotocol PCS
Autonegotiation GMII (GbE) and
Rate Adaptation for 10/100 MII Frames XGMII Interfaces to FPGA Fabric
8-bit GMII MAC Interface
10GbE MAC flexiMAC
Tri-Speed MAC
Platform: Platform:
Platform:
Soft IP Implemented on
Soft IP
TM
Compliant to IEEE802.3ae-2002 MACO Structured flexiMAC
10/100/1000 Mbps Operation
Optional HiGig/+ Capability for Broadcom ASIC Technology
Compliant to IEEE 802.3z
Multiprotocol Engine
StrataXGS I/II Switches (LatticeSC only) Can be Configured as
Generic FIFO Interface
XAUI or XGMII Interface a 10G or 1G MAC
Programmable IPG
System Aide FIFO Interface Saves Up to 5K LUTs in FPGA Real Estate
TX and RX Statistics Vectors
Programmable IPG Low Power Implementation (100mW max)
Multicast Address Filtering
TX and RX Statistics Vectors No IP Licensing Fees
MII/GMII Interface
Multicast Address Filtering
Management Interface
MDIO Interface
FCS on TX and RX
2.5GbE MAC
Supports:
Supports:
Full duplex control with PAUSE frames Platform:
Full Duplex control with PAUSE frames
VLAN tagged frames
VLAN tagged frames
Soft IP Bundle
Automatic padding of short frames
Automatic padding of short frames
10/100/1000 Mbps Operation
FCS on TX and RX
Automatic re-transmission on collision
Compliant to IEEE 802.3z
Jumbo packets
Broadcast and multicast frames
Jumbo packets (up to 8192 bytes)
Generic FIFO interface
Programmable IPG
TRI-SPEED MAC BLOC k D IAgRAM
TX and RX Statistics Vectors
Multicast Address Filtering
MII/GMII Interface
G/MII
Management Interface
FCS on TX and RX
Supports:
Receive
and
Full Duplex control with PAUSE frame
Host
Transmit
VLAN tagged frames
Interface
MAC
Automatic padding of short frames
Automatic re-transmission on collision
Broadcast and multicast frames
Jumbo packets
Management
Interface
Soft SPI4.2
MACO SPI4.2 XAUI to SPI4.2 Fabric
Platform:
Platform:
Interface
Industry Best Performance
Implemented on MACO Structured ASIC
Platform:
High performance FPGAs: LatticeSC/M at 1Gbps
Technology
Hard and Soft IP Bundle
with dynamic alignment
Very Low Power (0.85W)
Bundle Includes:
Industry best perfromance for low-cost FPGAs:
No-charge Bridge Reference design with source
Saves 4K LUTs in FPGA LUTs LatticeECP3, ECP2/M (750Mbps with static
code
alignment)
Maximum 1Gbps Bandwidth
SPI4.2 MACO (No IP licensing fee)
Support for 256 Logic Channels
No IP Licensing Fee
10GbE MAC IP
Highly Configurable
Optional HiGig+ Capability for
MACO SPI4.2 BLOC k D IAgRAM Selectable 64/128b bus width
Broadcom StrataXGS I/II Switches
Run-time user controls for TX idles, packing and
LatticeSCM Device
training patterns
Single Instance Fits into LatticeSC15
Programmable internal FIFO thresholds
SPI4.2 MACO IP Core
Device
Variable minimum burst sizes
17x17 256fpBGA industry's smallest footprint (by
ASIC FPGA Array
Variable packet sizes
40%)
Gates
Selectable status reporting (RAM or Transparent)
Lowest power SERDES at 3.125Gbps (105mW)
S4TX
User
Data Path
Lowest power SPI4.2 implementation (0.85W)
Logic
PHY
Status Path
Link Layer
Maximum Bandwidth of 12.5Gbps
Layer
Function
S4RX
Device
Tested with Broadcom StrataXGS Switches
or SPI4
Data Path
Loop
Status Path
Lattice Developed and Supported
SMI
Control
Regs SYSBUS
Physical Coding
System Interfaces Media Access Controllers
Sub-Layer