DMA-SG-CNX-UT Lattice

Scatter-Gather Direct Memory Access Controller IP Core User Guide March 2015 IPUG67_1.8Table of Contents Chapter 1. Introduction .......................................................................................................................... 4 Quick Facts ........................................................................................................................................................... 4 Features....................................................................................................................................................... 4 Chapter 2. Functional Description ........................................................................................................ 5 Key Concepts........................................................................................................................................................ 5 Block Diagram.............................................................................................................................................. 6 WISHBONE Interfaces................................................................................................................................. 6 Control and Status ....................................................................................................................................... 6 Channel Arbiter ............................................................................................................................................ 7 BDRAM Interface ......................................................................................................................................... 7 PBUFF Interface .......................................................................................................................................... 7 DMA Engine................................................................................................................................................. 7 Buffer Status Mode ...................................................................................................................................... 8 AUXCTRL and AUXSTAT............................................................................................................................ 9 Primary I/O................................................................................................................................................... 9 System Configurations............................................................................................................................... 11 Interface Descriptions ................................................................................................................................ 13 Registers and Memory............................................................................................................................... 15 Transaction Scenarios ............................................................................................................................... 18 Requirements and Guidelines.................................................................................................................... 20 Chapter 3. Parameter Settings ............................................................................................................ 22 User Parameters Tab.......................................................................................................................................... 23 Buses ......................................................................................................................................................... 23 Address Decoding...................................................................................................................................... 24 Channels.................................................................................................................................................... 24 Memory Interfaces ..................................................................................................................................... 25 Generation Options.................................................................................................................................... 25 Synthesis Optimizations Tab............................................................................................................................... 25 Transfer Settings........................................................................................................................................ 26 Chapter 4. IP Core Generation............................................................................................................. 28 IP Core Generation in IPexpress ........................................................................................................................ 28 Licensing the IP Core................................................................................................................................. 28 Getting Started........................................................................................................................................... 28 IPexpress-Created Files and Top Level Directory Structure...................................................................... 30 Simulation Evaluation................................................................................................................................. 31 Implementation Evaluation......................................................................................................................... 32 SGDMAC Core Implementation................................................................................................................. 32 IP Core Implementation ............................................................................................................................. 33 Hardware Evaluation.................................................................................................................................. 34 Updating/Regenerating the IP Core........................................................................................................... 34 IP Core Generation in Clarity Designer............................................................................................................... 35 Getting Started........................................................................................................................................... 35 Clarity Designer Created Files and Top Level Directory Structure ............................................................ 39 Simulation Evaluation................................................................................................................................. 39 IP Core Implementation ............................................................................................................................. 40 Regenerating/Recreating the IP Core ................................................................................................................. 41 Regenerating an IP Core in Clarity Designer Tool..................................................................................... 41 Recreating an IP Core in Clarity Designer Tool ......................................................................................... 41 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG67_1.8, March 2015 2 Scatter-Gather DMAC User Guide