ispXPGA Family July 2005 Data Sheet Microprocessor conguration interface Non-volatile, Innitely Recongurable 2 Instant-on - Powers up in microseconds via Program E CMOS while operating from SRAM 2 on-chip E CMOS based memory Eight sysCLOCK Phase Locked Loops No external conguration memory (PLLs) for Clock Management Excellent design security, no bit stream to intercept True PLL technology Recongure SRAM based logic in milliseconds 10MHz to 320MHz operation Clock multiplication and division High Logic Density for System-level Integration Phase adjustment 139K to 1.25M system gates Shift clocks in 250ps steps 160 to 496 I/O sysIO for High System Performance 1.8V, 2.5V, and 3.3V V operation CC High speed memory support through SSTL and Up to 414Kb sysMEM embedded memory HSTL High Performance Programmable Function Advanced buses supported through PCI, GTL+, Unit (PFU) LVDS, BLVDS, and LVPECL Four LUT-4 per PFU supports wide and narrow Standard logic supported through LVTTL, functions LVCMOS 3.3, 2.5 and 1.8 Dual ip-ops per LUT-4 for extensive pipelining 5V tolerant I/O for LVCMOS 3.3 and LVTTL Dedicated logic for adders, multipliers, multiplex- interfaces ers, and counters Programmable drive strength for series termination Flexible Memory Resources Programmable bus maintenance Multiple sysMEM Embedded RAM Blocks Two Options Available Single port, Dual port, and FIFO operation High-performance sysHSI (standard part number) 64-bit distributed memory in each PFU Low-cost, no sysHSI (E-Series) Single port, Double port, FIFO, and Shift sysHSI Capability for Ultra Fast Serial Register operation Communications Flexible Programming, Reconguration, Up to 800Mbps performance and Testing Up to 20 channels per device Supports IEEE 1532 and 1149.1 Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES) Table 1. ispXPGA Family Selection Guide ispXPGA 125/E ispXPGA 200/E ispXPGA 500/E ispXPGA 1200/E System Gates 139K 210K 476K 1.25M PFUs 484 676 1764 3844 LUT-4s 1936 2704 7056 15376 Logic FFs 3.8K 5.4K 14.1K 30.7K sysMEM Memory 92K 111K 184K 414K Distributed Memory 30K 43K 112K 246K EBR 20 24 40 90 1 sysHSI Channels 4 8 12 20 User I/O 160/176 160/208 336 496 Packaging 256 fpBGA 256 fpBGA 2 2 2 516 fpBGA 516 fpBGA 516 fpBGA 2 680 fpSBGA 900 fpBGA 900 fpBGA 1. E-Series does not support sysHSI. 2. Thermally enhanced package. 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1 xpga 12.0 Includes High- Performance, Low-Cost E-Series Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Family Overview The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that are both non-volatile and innitely re-programmable. Other FPGA solutions force a compromise, being either re- programmable or non-volatile. This family couples this capability with a mainstream architecture containing the fea- tures required for todays system-level design. The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications while the lower-cost E-Series supports the same high-performance FPGA fabric without the sysHSI Block. 2 Electrically Erasable CMOS (E CMOS) memory cells provide the ispXPGA family with non-volatile capability. These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica- tions. This capability also means that expensive external conguration memories are not required and that designs can be secured from unauthorized read back. Internal SRAM cells allow the device to be innitely recongured if 2 desired. Both the SRAM and E CMOS cells can be programmed and veried through the IEEE 1532 industry stan- dard. Additionally, the SRAM cells can be congured and read-back through the sysCONFIG peripheral port. The family spans the density and I/O range required for the majority of todays logic designs, 139K to 1.25M system gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, provid- ing easy integration into the overall system. System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are sup- ported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization (SERDES). The ispLEVER design tool from Lattice allows easy implementation of designs using the ispXPGA product. Syn- thesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these common synthesis packages and place and routes the design in the ispXPGA product. The tool supports oor planning and the management of other constraints within the device. The tool also provides outputs to common timing analysis tools for timing analysis. To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces, and memory controllers. Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design- ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz. Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly used by logic designers. Table 2. ispXPGA Speed Performance for Typical Building Blocks Function Performance 8:1 Asynch MUX 150 MHz 1:32 Asynch Demultiplexer 125 MHz 8 x 8 2-LL Pipelined Multiplier 225 MHz 32-bit Up/Down Counter 290 MHz 32-bit Shift Register 360 MHz 2