XRT75VL00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET SEPTEMBER 2008 REV. 1.0.4 GENERAL DESCRIPTION On-chip clock synthesizer provides the appropriate rate clock from a single 12.288 MHz Clock. The XRT75VL00D is a single-channel fully integrated Provides low jitter output clock. Line Interface Unit (LIU) with Sonet Desynchronizer for E3/DS3/STS-1 applications. It incorporates an TRANSMITTER: independent Receiver, Transmitter and Jitter Compliant with Bellcore GR-499, GR-253 and ANSI Attenuator in a single 52 pin TQFP package. T1.102 Specification for transmit pulse The XRT75VL00D can be configured to operate in Tri-state Transmit output capability for redundancy either E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 applications (51.84 MHz) modes. The transmitter can be turned off (tri-stated) for redundancy support and for Transmitter can be turned on or off. conserving power. JITTER ATTENUATOR: The XRT75VL00Ds differential receiver provides high On chip advanced crystal-less Jitter Attenuator. noise interference margin and is able to receive the data over 1000 feet of cable or with up to 12 dB of Jitter Attenuator can be selected in Receive or cable attenuation. Transmit paths. The XRT75VL00D incorporates an advanced crystal- 16, 32 or 128 bits selectable FIFO size. less jitter attenuator that can be selected either in the Meets the Jitter and Wander specifications transmit or receive path. The jitter attenuator described in T1.105.03b,ETSI TBR-24, Bellcore performance meets the ETSI TBR-24 and Bellcore GR-253 and GR-499 standards. GR-499 specifications. Also, the jitter attenuator can be used for clock smoothing in SONET STS-1 to DS3 Jitter Attenuator can be disabled. de-mapping. De-Synchronizer for SONET STS-1 to DS-3 The XRT75VL00D provides both Serial demapping. Microprocessor Interface as well as Hardware mode CONTROL AND DIAGNOSTICS: for programming and control. 5 wire Serial Microprocessor Interface for control The XRT75VL00D supports local, remote and digital and configuration. loop-backs. The XRT75VL00D also contains an on- board Pseudo Random Binary Sequence (PRBS) Supports optional internal Transmit Driver generator and detector with the ability to insert and Monitoring. detect single bit error. PRBS error counter register to accumulate errors. FEATURES Hardware Mode for control and configuration. RECEIVER: Supports Local, Remote and Digital Loop-backs. On chip Clock and Data Recovery circuit for high Single 3.3 V 5% power supply. input jitter tolerance. 5 V Tolerant I/O. Meets E3/DS3/STS-1 Jitter Tolerance Requirements. Available in 52 pin TQFP. Detects and Clears LOS as per G.775. -40C to 85C Industrial Temperature Range. Meets Bellcore GR-499 CORE Jitter Transfer APPLICATIONS Requirements. E3/DS3 Access Equipment. Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation. DSLAMs. Compliant with jitter transfer template outlined in Digital Cross Connect Systems. ITU G.751, G.752, G.755 and GR-499-CORE,1995 CSU/DSU Equipment. standards. Routers. Meets ETSI TBR 24 Jitter Transfer Requirements. Fiber Optic Terminals. On chip B3ZS/HDB3 encoder and decoder that can be either enabled or disabled. Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT75VL00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.4 FIGURE 1. BLOCK DIAGRAM OF THE XRT 75VL00D SDI CLK OUT XRT75L03 SDO Serial ExClk/12M INT Processor SClk Interface RLOL CS RxON RESET RxClkINV Clock HOST/HW Invert RxClk Synthesizer Peak Detector STS-1/DS3 E3 HDB3/ RPOS REQEN Clock & Data Jitter Slicer B3ZS AGC/ MUX RNEG/ RTIP Recovery Attenuator Decoder Equalizer LCV RRING LOS SR/DR Remote Detector Local LLB LoopBack RLB LoopBack RLOS JATx/Rx TTIP TPData HDB3/ Line Tx Jitter Timing B3ZS Driver MUX TNData Pulse Attenuator TRING Encoder Control Shaping TxClk TAOS MTIP Device MRING Tx Monitor TxLEV Control TxON DMO Note: Serial Processor Interface input pins are shared by inHos Mode and redefined in theHardwar Mode. TRANSMIT INTERFACE CHARACTERISTICS Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line Integrated Pulse Shaping Circuit. Built-in B3ZS/HDB3 Encoder (which can be disabled). Accepts Transmit Clock with duty cycle of 30%-70%. Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications. Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and ANSI T1.102 1993. Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE. Transmitter can be turned off in order to support redundancy designs. RECEIVE INTERFACE CHARACTERISTICS Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery. Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications. Meets Jitter Tolerance Requirements, as specified in ITU-T G.823 1993 for E3 Applications. Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications. Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms. Built-in B3ZS/HDB3 Decoder (which can be disabled). Recovered Data can be muted while the LOS Condition is declared. 2