XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT MARCH 2010 REV. 2.0.0 The on-chip clock synthesizer generates an E1 clock GENERAL DESCRIPTION reference. The XRT83VSH28 is a fully integrated 8-channel Additional features include RLOS, a 16-bit LCV short-haul line interface unit (LIU) that operates from counter for each channel, AIS, QRSS generation/ a 1.8V and a 3.3V power supply. Using internal detection, TAOS, DMO, and diagnostic loopback termination, the LIU provides one bill of materials to modes. operate in E1 75 or 120 mode with minimum external components. The LIU features are APPLICATIONS programmed through a standard parallel or serial ISDN Primary Rate Interface microprocessor interface. EXARs LIU has patented high impedance circuits that allow the transmitter CSU/DSU E1 Interface outputs and receiver inputs to be high impedance E1 LAN/WAN Routers when experiencing a power failure or when the LIU is powered off. Key design features within the LIU Public switching Systems and PBX Interfaces optimize 1:1 or 1+1 redundancy and non-intrusive E1 Multiplexer and Channel Banks monitoring applications to ensure reliability without using relays. FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH28 E1 LIU (HOST MODE) MCLKOUT MCLKE1 MASTER CLOCK SYNTHESIZER DRIVE 1 of 8 channels, CHANNEL n TAOS DMO n MONITOR TPOS n/ TDATA n TTIP n QRSS HDB3/ TX FILTER TX/ RX JITTER TIMING LINE TNEG n/ CODES n PATTERN & PULSE ENCODER ATTENUATOR CONTROL DRIVER GENERATOR SHAPER TCLK n TRING n TXON n Remote Digital Analog Loopback Loopback Loopback QRSS DETECTOR RCLK n HDB3/ TIMING & PEAK RTIP n TX/ RX JITTER RNEG n/LCV n DATA DETECTOR DECODER ATTENUATOR RECOVERY & SLICER RPOS n/ RDATA n RRING n LOS AIS DETECTOR DETECTOR RLOS n TEST ICT HW/ HOST PTS1 WR R/W PTS2 RD DS ALE-AS D 7:0 MICROPROCESSOR/ SERIAL INTERFACE CONTROLLER CS PCLK/ SCLK RDY DTACK/ SDO A 7:0 /SDI INT RESET SER PAR Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT83VSH28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 2.0.0 FIGURE 2. BLOCK DIAGRAM OF THE XRT83VSH28 E1 LIU (HARDWARE MODE) MCLKOUT MCLKE1 MASTER CLOCK SYNTHESIZER TAOS n DRIVE 1 of 8 channels, CHANNEL n TAOS MONITOR DMO n TPOS n/ TDATA n QRSS HDB3/ TX FILTER TTIP n TX/ RX JITTER TIMING LINE PATTERN & PULSE TNEG n/ CODES n ENCODER ATTENUATOR CONTROL DRIVER GENERATOR SHAPER TCLK n TRING n Remote Digital Analog TXON n Loopback Loopback Loopback QRSS DETECTOR HDB3/ TIM ING & PEAK RCLK n TX/ RX JITTER RTIP n DATA DETECTOR RNEG n/LCV n DECODER ATTENUATOR RECOVERY & SLICER RRING n RPOS n/ RDATA n LOOP1 n LOS AIS LOOP0 n DETECTOR DETECTOR RLOS n TEST ICT HW/ HOST GAUGE RESET TRATIO JASEL1 SR/DR JASEL0 EQC 4:0 RXTSEL HARWARE CONTROL TXTSEL TCLKE RCLKE TERSEL RXMUTE RXRES0 ATAOS RXRES1 2