DSC557-05 Crystal-less Four Output PCIe Clock Generator General Description Features The DSC557-05 is a Crystal-less , four Meets PCIe Gen1, Gen2 & Gen3 specs output PCI express clock generator meeting Gen1, Gen2, and Gen3 specifications. The Available Output Formats: clock generator uses proven silicon MEMS o HCSL, LVPECL, or LVDS technology to provide excellent jitter and o Mixed Outputs: LVPECL/HCSL/LVDS stability over a wide range of supply voltages and temperatures. By eliminating Wide Temperature Range the external quartz crystal, MEMS clock o Ext. Industrial: -40 to 105 C generators significantly enhance reliability o Industrial: -40 to 85 C and accelerate product development, while meeting stringent clock performance criteria o Ext. commercial: -20 to 70 C for a variety of communications, storage, and networking applications. Supply Range of 2.25 to 3.6 V Low Power Consumption DSC557-05 has an Output Enable / Disable o 30% lower than competing devices feature allowing it to disable all outputs when OE1 and OE2 are low. Each output Excellent Shock & Vibration Immunity enable pin controls two banks of o Qualified to MIL-STD-883 synchronous PCIe clocks. See the OE function diagram for more detail. The Available Footprints: device is available in a 20 pin QFN. o 20 QFN Additional output formats are in any Lead Free & RoHS Compliant combination of LVPECL, LVDS, and HCSL. Short Lead Time: 2 Weeks Block Diagram Applications Communications/Networking o Ethernet o 1G, 10GBASE-T/KR/LR/SR, and FcoE o Routers and Switches o Gateways, VoIP, Wireless APs o Passive Optical Networks Storage o SAN, NAS, SSD, JBOD Embedded Applications o Industrial, Medical, and Avionics * Clk0+/-, Clk1+/-, Clk2 +/- and Clk3 +/- are o Security Systems and Office 100 MHz as per PCIe standards. For other Automation frequencies, please contact the factory. o Digital Signage, POS and others Consumer Electronics o Smart TV, Bluray, STB DSC557-05 Page 1 Crystal-less Four Output PCIe Clock Generator DSC557-05 Specifications (Unless specified otherwise: T=25 C, VDD =3.3V) Parameter Condition Min. Typ. Max. Unit 1 Supply Voltage V 2.25 3.6 V DD EN pin low outputs are Supply Current I 42 46 mA DD disabled EN pin high outputs are 2 Supply Current enabled I 120 mA DD (Four HCSL Outputs) R =50 , L F =F =F = F =100 MHz O1 O2 O3 O4 Includes frequency variations 100 Frequency Stability f due to initial tolerance, temp. ppm 50 and power supply voltage 3 Startup Time t T=25C 5 ms SU Input Logic Levels Input logic high V 0.75xV - V IH DD Input logic low V - 0.25xV IL DD 4 Output Disable Time t 5 ns DA Output Enable Time t 20 ns EN 2 Pull-Up Resistor Pull-up on OE pin 40 k 6 HCSL Outputs Parameter Condition Min. Typ. Max. Unit Output Logic Levels Output logic high V R =50 0.725 - V OH L Output logic low V - 0.1 OL Pk to Pk Output Swing Single-Ended 750 mV 4 Output Transition time 20% to 80% Rise Time t 200 400 ps R R =50 , C = 2pF L L Fall Time t F 7 Frequency f Single Frequency 2.3 100 460 MHz 0 Output Duty Cycle SYM Differential 48 52 % 5 Period Jitter J F =F = F = F =100 MHz 2.5 ps PER O1 O2 O3 O4 RMS 8 T PCIe Gen 1.1 22.7 86.0 ps J p-p Jitter, Phase 8 (Common Clock J PCIe Gen 2.1, 1.5MHz to Nyquist 2.20 3.1 ps RMS-CCHF RMS Architecture) 8 J PCIe Gen 2.1, 10 kHz to 1.5 MHz 0.08 3.0 ps RMS-CCLF RMS 8 J PCIe Gen 3.0 0.37 1.0 ps RMS-CC RMS 8 J PCIe Gen 2.1, 1.5MHz to Nyquist 2.15 4.0 ps Integrated Phase Noise RMS-DCHF RMS 8 (Data Clock J PCIe Gen 2.1, 10 kHz to 1.5 MHz 0.06 7.5 ps RMS-DCLF RMS Architecture) 8 J PCIe Gen 3.0 0.32 1.0 ps RMS-DC RMS Notes: 1. Each V pin should be filtered with 0.01uf capacitor. DD 2. Output is enabled if OE pin is floated or not connected. 3. t is time to 100PPM stable output frequency after V is applied and outputs are enabled. su DD 4. Output Waveform and Connection Diagram define the parameters. 5. Period Jitter includes crosstalk from adjacent output. 6. Contact Sales Discera.com for alternate output options (LVPECL, LVDS, LVCMOS). 7. Contact Sales Discera.com for alternative frequency options 8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards. DSC557-05 Page 2