8983 VECTRON 06/17/02 12:13 PM Page 1 Product Data Sheet FX-700 Low Jitter Frequency Translator Features 5.0 x 7.5 mm, Hermetically sealed SMD package Frequency Translation to 77.760 MHz 3.3 Volt or 5.0 Volt Supply Tri-State Output allows board test Lock Detect Commercial or Industrial Temp. Range CMOS Output Absolute Pull Range Performance to +/-100 ppm Capable of locking to an 8 kHz pulse/BITS clock Description Applications The FX-700 is a crystal-based frequency translator Frequency Translation, Clock Smoothing used in communications applications where low jit- Telecom - SONET/SDH/ATM ter is paramount. Datacom DSLAM, DSLAR, Access Nodes Performance advantages include superior jitter Base Station GSM, CDMA performance, high output frequencies and small Cable Modem Head End package size. Advanced custom ASIC technology results in a highly robust, reliable and predictable device. The device is packaged in a 16 pad ceram- ic package with a hermetic seam welded lid. R2 External Loop Filter C1 C2 C1 Charge Pump Out (5) V (16) CIN V (3) COUT LD (8) F (6) IN Charge Phase/Freq. VCXO Pump Buffer Input Frequency Detector VCXO Divider (1-64) OUT (13) Output Frequency Buffer Divider (1-16384) FX-700 FOUT (10) VCXO (12) IN Tri-State (4) GND (7) V (2) V (1) VDB (11) GND (9) DA VDO (14) DD B Figure 1. FX-700 Block Diagram8983 VECTRON 06/17/02 12:13 PM Page 2 FX-700 Low Jitter Frequency Translator Performance Characteristics Electrical Performance Parameter Symbol Minimum Typical Maximum Units 4 Output Frequency Output (3.3 V) fo 0.100 77.760 MHz Output (5.0 V) fo 0.100 77.760 MHz 1 Supply Voltage (VDD,VDB,VDA,VDO) +5.0 VDD 4.5 5.0 5.5 V +3.3 VDD 2.97 3.3 3.63 V 5 Supply Current 19.440 MHz IDD 15 20 mA 49.152 MHz IDD 25 30 mA 77.760 MHz IDD 35 40 mA 2 Output Output High VOH 0.9*Vdd V Output Low VOL 0.1*Vdd V 2 Transition Times Rise Time tR 1.8 3.0 ns Fall Time tF 1.8 3.0 ns 3 Duty Cycle <60 MHz D 45 50 55 % 60 MHz 40 50 60 % Absolute Pull Range APR See Part Numbering ppm Operating Temperature: 0 to 70C or -40 to 85C Test Conditions for APR (+5V option) VC 0.5 4.5 V Test Conditions for APR (+3.3V option) VC 0.3 3.0 V Input Frequency fIN 1 kHz 77.76 MHz Pulse Width 6.0 ns Low Logic Level VIL 0.3* Vdd V High Logic Level VIH 0.7* Vdd V 6 Jitter, 8kHz to 77.760 MHz rms 4.7 ps peak/peak 44 ps peak/peak 0.003 UI Leakage Current of Input IC -1 +1 uA Size 5.0mm x 7.5mm x 2.0mm 1. A 0.01uF high frequency ceramic capacitor in parallel with a 0.1uF low frequency tantalum bypass capacitor is recommended 2. Figure 2 defines the waveform parameters. Figure 3 illustrates the standard test conditions under which these parameters are tested and specified 3. Duty Cycle is defined as (on time/period) with Vs = Vdd/2 per Figure 2. Duty Cycle is measured with a 15pf load per Figure 3. 4. Other frequencies may be available, please contact factory. 5. Combined Current From V , V , V , and V DD DO DA DB 6. Typical jitter for 8 kHz to 77.760 MHz translation (no offset bandwidth). 30k 2k I DD t t F R 80% 2,14,11,1 8 13,12 10 + V .1uF .01uF Vs DD 15 6 4 7,9 3,16 5 - 20% n/c On Time 15pF R2 f IN C1 C2 Period Figure 2. Output Waveform Figure 3. Output Test Conditions (25 5C) Vectron International 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 Web: www.vectron.com 2