LAN9115 Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Reduced Power Modes Highlights - Numerous power management modes Member of LAN9118 Family optimized for - Wake on LAN* medium-performance applications - Magic packet wakeup* Easily interfaces to most 16-bit embedded CPUs - Wakeup indicator event signal Efficient architecture with low CPU overhead - Link Status Change Integrated PHY supports external PHY via MII Single chip Ethernet controller interface - Fully compliant with IEEE 802.3/802.3u stan- Supports audio & video streaming over Ethernet: dards multiple standard-definition (SD) MPEG2 streams - Integrated Ethernet MAC and PHY - 10BASE-T and 100BASE-TX support Medium-speed member of LAN9118 Family (all members are pin-compatible) - Full- and Half-duplex support - Full-duplex flow control - Backpressure for half-duplex flow control Target Applications - Preamble generation and removal Printers, kiosks, security systems - Automatic 32-bit CRC generation and check- ing General embedded applications - Automatic payload padding and pad removal Audio distribution systems - Loop-back modes Basic Cable, satellite, and IP set-top boxes Flexible address filtering modes Video-over IP Solutions, IP PBX & Video Phones - One 48-bit perfect address Wireless routers & access points - 64 hash-filtered multicast addresses Digital video recorders - Pass all multicast - Promiscuous mode Key Benefits - Inverse filtering - Pass all incoming with status report Non-PCI Ethernet controller for medium-perfor- - Disable reception of broadcast packets mance applications Integrated Ethernet PHY - 16-bit interface - Auto-negotiation - Burst-mode read support - Automatic polarity detection and correction - External MII Interface High-Performance host bus interface Eliminates dropped packets - Simple, SRAM-like interface - Internal SRAM can store over 200 packets - 16-bit data bus - Supports automatic or host-triggered PAUSE - Large, 16Kbyte FIFO memory that can be and back-pressure flow control allocated to RX or TX functions Minimizes CPU overhead - One configurable host interrupt - Supports Slave-DMA Miscellaneous features - Interrupt Pin with Programmable Hold-off - Low profile 100-pin, TQFP RoHS Compliant timer package Reduces system cost and increases design flexi- - Integral 1.8V regulator bility - General Purpose Timer - SRAM-like interface easily interfaces to most - Support for optional EEPROM Embedded CPUs or SoCs - Support for 3 status LEDs multiplexed with - Low-cost, low--pin count non-PCI interface Programmable GPIO signals for embedded designs 3.3V Power Supply with 5V tolerant I/O 0 to 70 C * Third-party brands and names are the property of their respective owners. 2005-2018 Microchip Technology Inc. DS00002269B-page 1LAN9115 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: