PIC18(L)F24/25K42 28-Pin, Low-Power High-Performance Microcontrollers with XLP Technology Description The PIC18(L)F24/25K42 microcontrollers are available in 28-pin devices. These devices feature a 12-bit ADC with 2 Computation (ADC ) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and threshold comparison, Temperature Sensor, Vectored Interrupt Controller with fixed latency for handling interrupts, System Bus Arbiter, Direct Memory Access capabilities, UART with support for Asynchronous, 2 DMX, DALI and LIN transmissions, SPI, I C, memory features like Memory Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy. Core Features Memory C Compiler Optimized RISC Architecture Up to 128 KB Flash Program Memory Up to 8 KB Data SRAM Memory Operating Speed: Up to 1 KB Data EEPROM - Up to 64 MHz clock input Memory Access Partition (MAP) - 62.5 ns minimum instruction cycle - Configurable boot and app region sizes with Two Direct Memory Access (DMA) Controllers individual write-protections - Data transfers to SFR/GPR spaces from Programmable Code Protection either Program Flash Memory, Data Device Information Area (DIA) stores: EEPROM or SFR/GPR spaces - Unique IDs and Device IDs - User-programmable source and destination - Temp Sensor factory-calibrated data sizes - Fixed Voltage Reference calibrated data - Hardware and software-triggered data Device Configuration Information (DCI) stores: transfers - Erase row size System Bus Arbiter with User-Configurable - Number of write latches per row Priorities for Scanner and DMA1/DMA2 with - Number of user rows respect to the main line and interrupt execution - Data EEPROM memory size Vectored Interrupt Capability - Pin count - Selectable high/low priority - Fixed interrupt latency Operating Characteristics - Programmable vector table base address Operating Voltage Range: 31-Level Deep Hardware Stack - 1.8V to 3.6V (PIC18LF24/25K42) Low-Current Power-on Reset (POR) - 2.3V to 5.5V (PIC18F24/25K42) Configurable Power-up Timer (PWRT) Temperature Range: Brown-Out Reset (BOR) - Industrial: -40C to 85C Low-Power BOR (LPBOR) Option - Extended: -40C to 125C Windowed Watchdog Timer (WWDT) - Variable prescaler selection - Variable window size selection Power-Saving Functionality - Configurable in hardware or software Doze mode: Ability to run CPU core slower than the system clock Idle mode: Ability to halt CPU core while internal peripherals continue operating Sleep mode: Lowest power consumption Peripheral Module Disable (PMD): - Ability to disable unused peripherals to minimize power consumption 2016-2020 Microchip Technology Inc. DS40001869E-page 1PIC18(L)F24/25K42 One SPI module: eXtreme Low-Power (XLP) Features - Configurable length bytes Sleep mode: 60 nA 1.8V, typical - Configurable length data packets Windowed Watchdog Timer: 720 nA 1.8V, - Receive-without-transmit option typical - Transmit-without-receive option Secondary Oscillator: 580 nA 32 kHz - Transfer byte counter Operating Current: - Separate Transmit and Receive Buffers with - 4 uA 32 kHz, 1.8V, typical 2-byte FIFO and DMA capabilities 2 - 45 uA/MHz 1.8V, typical Two I C modules, SMBus, PMBus compatible: - Supports Standard-mode (100 kHz), Fast- Digital Peripherals mode (400 kHz) and Fast-mode plus (1 MHz) modes of operation Three 8-Bit Timers (TMR2/4/6) with Hardware - Dedicated Address, Transmit and Receive Limit Timer (HLT) buffers - Hardware monitoring and Fault detection - Bus Collision Detection with arbitration Four 16-Bit Timers (TMR0/1/3/5) - Bus time-out detection and handling Four Configurable Logic Cell (CLC): - Multi-Master mode - Integrated combinational and sequential logic - Separate Transmit and Receive Buffers with Three Complementary Waveform Generators 2-byte FIFO and DMA capabilities (CWGs): 2 -I C, SMBus 2.0 and SMBus 3.0, and 1.8V - Rising and falling edge dead-band control input level selections - Full-bridge, half-bridge, 1-channel drive Device I/O Port Features: - Multiple signal sources - 24 I/O pins - Programmable dead band - One input-only pin (RE3) - Fault-shutdown input - Individually programmable I/O direction, Four Capture/Compare/PWM (CCP) modules open-drain, slew rate, weak pull-up control Four 10-bit Pulse-Width Modulators (PWMs) - Interrupt-on-change (on up to 25 I/O pins) Numerically Controlled Oscillator (NCO): - Three External Interrupt Pins - Generates true linear frequency control Peripheral Pin Select (PPS): - High resolution using 20-bit accumulator and - Enables pin mapping of digital I/O 20-bit increment values Signal Measurement Timer (SMT): DSM: Data Signal Modulator - 24-bit timer/counter with prescaler - Multiplex two carrier clocks, with glitch prevention feature - Multiple sources for each carrier Programmable CRC with Memory Scan: - Reliable data/program memory monitoring for fail-safe operation (e.g., Class B) - Calculate CRC over any portion of program memory or data EEPROM Two UART Modules: - Modules are asynchronous and compatible with RS-232 and RS-485 - One of the UART modules supports LIN Master and Slave, DMX-512 mode, DALI Gear and Device protocols - Automatic and user-timed BREAK period generation - DMA Compatible - Automatic checksums - Programmable 1, 1.5, and 2 Stop bits - Wake-up on BREAK reception 2016-2020 Microchip Technology Inc. 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