PL133-37
Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC
FEATURES DESCRIPTION
The PL133-37 is an advanced fanout buffer design
3 LVCMOS Outputs
for high performance, low-power, small form-factor
12mA Output Drive Strength
applications. The PL133-37 accepts a reference
Input/Output Frequency:
clock input of 1MHz to 150MHz and produces three
o Reference Clock: 1MHz to 150MHz
outputs of the same frequency. Reference clock in-
Supports LVCMOS or Sine Wave Input Clock
puts may be LVCMOS or sine-wave signals (the in-
Very Low Jitter and Phase Noise
puts are internally AC-coupled). Offered in a small
Low Current Consumption
3mm x 3mm SOT23, the PL133-37 offers the best
Single 1.8V, 2.5V, or 3.3V, 10% Power Supply
phase noise and jitter performance and lowest power
Operating Temperature Range
consumption of any comparable IC.
o 0C to 70C (Commercial)
o -40C to 85C (Industrial)
Available in SOT23-6L GREEN/RoHS Compliant
Packages
PACKAGE PIN CONFIGURATION
CLK1 1 6 CLK2
GND 2 5 VDD
FIN 3 4 CLK0
SOT23-6L
BLOCK DIAGRAM
CLK0
FIN CLK1
CLK2
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 02/24/15 Page 1 PL133-37
Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC
PIN DESCRIPTION
Package Pin #
Name Type Description
SOT23-6L
CLK1 1 O Output clock
GND 2 P Ground connection
FIN 3 I Reference clock input
CLK0 4 O Output clock
VDD 5 P Power supply
CLK2 6 O Output clock
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations
- Keep traces short! - Place decoupling capacitors as close as possible to
the V pin(s) to limit noise from the power supply
DD
- Trace = Inductor. With a capacitive load this equals
ringing! - Multiple V pins should be decoupled separately
DD
for best performance.
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections (looks like ringing). - Addition of a ferrite bead in series with V can
DD
help prevent noise from other board sources
- Design long traces as striplines or microstrips with
defined impedance. - Value of decoupling capacitor is frequency de-
pendant. Typical value to use is 0.1 F.
- Match trace at one side to avoid reflections bouncing
back and forth.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
To CMOS Input
(Typical buffer impedance 20)
50 line
Series Resistor
Use value to match output buffer impedance to
50 trace. Typical value 30
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 02/24/15 Page 2