SuperLite 2.5V/3.3V 2.5GHz Micrel, Inc. SY55856U SuperLite DIFFERENTIAL 2-CHANNEL SY55856U PRECISION CML DELAY LINE FEATURES Guaranteed AC parameters over temp and voltage SuperLite > 2.5GHz f MAX < 384ps prop delay DESCRIPTION < 120ps t /t r f Delay either clock or data The SY55856U is a 2.5GHz, two-channel, fully differential 50ps increments CML (Current Mode Logic) delay line. The device is optimized to adjust the relative delay between two channels, 350ps total delay such as clock and data, in 50ps increments. Both inputs Source terminated CML outputs may be adjusted in either direction in 7 increments of 50ps, Full differential I/O for a total adjustment range of 350ps. In addition, the Wide supply voltage spectrum: 2.3V to 3.6V clock input maybe inverted through the CINV control pin. The SY55856U inputs are designed to accept single- Available in a tiny 32-pin EPAD-TQFP package ended or differential CML signals. The differential CML outputs are optimized for 50 loads (50 source terminated), thus only requires a single 100 resistor across the output pair. Output rise and fall time is an extremely fast 110ps(max) APPLICATIONS and the differential swing is 400mV. The maximum throughput of the SY55856U is guaranteed to exceed Data communications systems 2.5GHz (5Gbps). Telecom systems High-speed backplanes Signal de-skewing Pulse alignment Digitally controlled delay lines SuperLite is a trademarks of Micrel, Inc. Rev.: F Amendment: /0 M9999-021908 1 Issue Date: February 2008 hbwhelp micrel.com or (408) 955-1690SuperLite Micrel, Inc. SY55856U PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead Part Number Type Range Marking Finish 32 31 30 29 28 27 26 25 SY55856UHI H32-1 Industrial 55856U Sn-Pb /DATA IN 1 24 /DATA OUT (2) GND 23 2 GND SY55856UHITR H32-1 Industrial 55856U Sn-Pb DATA IN 3 22 DATA OUT (3) SY55856UHG H32-1 Industrial 55856U with NiPdAu Top View GND 21 GND 4 Pb-Free bar line indicator Pb-Free EPAD-TQFP 20 GND 5 GND (2, 3) H32-1 SY55856UHGTR H32-1 Industrial 55856U with NiPdAu CLK IN 6 19 CLK OUT Pb-Free bar line indicator Pb-Free GND 18 GND 7 /CLK IN /CLK OUT 8 17 Notes: 9101112 13141516 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 3. Pb-Free package recommended for new designs. 32-Pin EPAD-TQFP (H32-1) PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 3 /DATA IN, CML Input (Differential). This is one of the CML inputs, the data in signal. A delayed DATA IN version of this signal appears at DATA OUT, /DATA OUT. 2, 4, 5, 7, GND Ground. 18, 20. 21, 23 22, 24 DATA OUT, CML Output (Differential). This is one of the CML outputs, the data output. It is a delayed /DATA OUT version of DATA IN , /DATA IN. 6, 8 CLK IN, CML Input (Differential). This is one of the differential CML inputs, the clock in signal. A /CLK IN delayed version of this input appears at CLK OUT, /CLK OUT. 17, 19 /CLK OUT, CML Output (Differential). This is one of the CML outputs, the clock output. It is a delayed, CLK OUT copy of CLK IN, /CLK IN. 9, 10, 15, 16 VCC Power Supply. 25, 26, 31, 32 11 CINV VT Input (Single Ended). This is the clock inversion select signal. This input optionally inverts the CLK IN, /CLK IN signal which results in an inverted CLK OUT, /CLK OUT. A voltage below the VT threshold results in no inversion. A voltage above the threshold value results in an inversion from the clock input to the clock output. Refer to the VT input section below. 14 LVL Analog Input. This input determines what level differentiates logic high from logic low. This input affects the behavior of the CINV, S0, S1 and S2 inputs. Please refer to the VT input section below for more details. For the control interface, see Figure 3a. For TTL control interface, see Figure 3b. 30 DELAY SEL VT Input (Single Ended). CML compatible control logic. This is the delay path control input. Logic high delays the clock signal with respect to the data signal. A logic low delays the data signal with respect to the clock signal. Inputs S2, S1 and S0 control amount of delay. 27, 28, 29 S0, S1, S2 VT Input (Single Ended). CML compatible control logic. This is the delay selection control input. These three bits define how much relative delay will occur between the data and clock signals, as per the truth table shown in Table 2. For the control logic interface, see Figure 3a. For TTL control interface, see Figure 3b. S0=LSB. 12, 13 NC No Connect. M9999-021908 2 hbwhelp micrel.com or (408) 955-1690 VCC VCC VCC VCC CINV DELAY SEL NC S2 NC S1 LVL S0 VCC VCC VCC VCC