SY56011RMG Microchip

SY56011R Low Voltage 1.2V/1.8V/2.5V CML 1:2 Fanout Buffer, 6.4 Gbps with Equalization Features General Description 1.2V/1.8V/2.5V CML 1:2 Fanout Buffer The SY56011R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:2 Fanout Buffer with input Equalizes 9, 18, 27 inches of FR4 equalization. The SY56011R can process clock signals Guaranteed AC Performance over Temperature as fast as 4.5 GHz or data patterns up to 6.4 Gbps. and Voltage: The differential input includes a unique, 3-pin input - DC- to > 6.4 Gbps Throughput termination architecture that interfaces to CML - DC- to > 4.5 GHz Clock Throughput differential signals, without any level-shifting or - <280 ps Propagation Delay (IN-to-Q) termination resistor networks in the signal path. The - <15 ps Within-Device Skew differential input can also accept AC-coupled LVPECL - <80 ps Rise/Fall Times and LVDS signals. Input voltages as small as 200 mV (400 mV ) are applied before the 9, 18, or 27 FR4 Ultra-Low Jitter Design PP transmission line. For AC-coupled input interface -1 ps Random Jitter RMS applications, an internal voltage reference is provided High Speed CML Outputs to bias the VT pin. The outputs are CML, with extremely 2.5V 5% V , 1.2V/1.8V/2.5V 5% V Power CC CCO fast rise/fall times guaranteed to be less than 80 ps. Supply Operation The SY56011R operates from a 2.5V 5% core supply Industrial Temperature Range: 40C to +85C and a 1.2V, 1.8V, or 2.5V 5% output supply and is Available in 16-pin (3 mm x 3 mm) QFN Package guaranteed over the full industrial temperature range (40C to +85C). The SY56011R is part of the high Applications speed, Precision Edge product line. Data Distribution: OC-48, OC-48+FEC Package Type SONET Clock and Data Distribution SY56011R Fibre Channel Clock and Data Distribution 16-Pin QFN Gigabit Ethernet Clock and Data Distribution (Top View) Markets Storage ATE Test and Measurement Enterprise Networking Equipment High-End Servers Access Metro Area Network Equipment 2019 Microchip Technology Inc. DS20006167A-page 1SY56011R Functional Block Diagram SY56011R 3 mm 3 mm QFN Q0 Equalization IN /Q0 V VT T /IN Q1 /Q1 EQ (3 level input) 2DS20006167A-page 2019 Microchip Technology Inc.