SY898533LKZ Microchip

SY898533L Precision Differential 3.3V Low-Skew LVPECL 1:4 Fanout Buffer Features General Description Provides Four Differential 3.3V LVPECL Copies The SY898533L is a 3.3V, low-skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most Selects between Differential CLK, /CLK, or standard differential input levels can be applied to the LVPECL Clock Inputs CLK, /CLK pair while LVPECL, CML, or SSTL input CLK, /CLK Pair Accepts LVDS, LVPECL, levels can be applied to the PCLK, /PCLK pair. To LVHSTL, SSTL, HCSL Input Levels eliminate runt pulses on the outputs during PCLK, /PCLK Pair Accepts LVPECL, CML, SSTL asynchronous assertion/deassertion of the clock Input Levels enable pin, the clock enable is synchronized with the Guaranteed AC Performance over Temperature input signal. and Supply Voltage: The SY898533L operates from a 3.3V 5% supply and - 650 MHz Maximum Output Frequency is guaranteed over the 0C to +70C temperature - <1.4 ns Propagation Delay (In-to-Q) range. The SY898533L is part of Microchips - <30 ps Output Skew high-speed, Precision Edge product line. - <150 ps Part-to-Part Skew - Additive Phase Jitter, RMS: 145 fs (Typical) Package Type 3.3V 5% Supply Voltage SY898533L 20-Lead TSSOP 0C to +70C Operating Temperature Range Available in a 20-Lead TSSOP Package VEE 1 20 Q0 Applications CLK EN 2 19 /Q0 SONET Clock Distribution CLK SEL 3 18 VCC Backplane Distribution CLK 4 17 Q1 Markets /CLK 5 16 /Q1 LAN/WAN PCLK 6 15 Q2 Enterprise Servers ATE /PCLK 7 14 /Q2 Test and Measurement NC 8 13 VCC NC 9 12 Q3 VCC 10 11 /Q3 2019 Microchip Technology Inc. DS20006043A-page 1SY898533L Functional Block Diagram D CLK EN Q LE CLK 0 /CLK Q0 PCLK /Q0 1 /PCLK Q1 /Q1 CLK SEL Q2 /Q2 Q3 /Q3 DS20006043A-page 2 2019 Microchip Technology Inc.