SY89874AU 2.5GHz, Any-In to LVPECL, Programmable Clock Divider/Fanout Buffer with Internal Termination General Description This low-skew, low-jitter device can accept a high-speed Precision Edge (622MHz or higher) LVTTL, LVCMOS, CML, LVPECL, Features LVDS or HSTL clock input signal and divide down the Integrated programmable clock divider and 1:2 fanout frequency using a programmable divider ratio to create a buffer frequency-locked, lower speed version of the input clock. Available divider ratios are 2, 4, 8, and 16, or straight Guaranteed AC performance over temperature and pass-through. In a typical 622MHz clock system this would voltage: provide availability of 311MHz, 155MHz, 77MHz, or > 2.5GHz f MAX 38MHz auxiliary clock components. < 250ps t /t r f The differential input buffer has a unique internal < 15ps within device skew termination design that allows access to the termination Low jitter design: network through a VT pin. This feature allows the device to easily interface to different logic standards. A V < 10ps total jitter REF-AC PP reference is included for AC-coupled applications. < 1ps cycle-to-cycle jitter RMS The /RESET input asynchronously resets the divider. In Unique input termination and VT pin for DC-coupled and the pass-through function (divide by 1) the /RESET AC-coupled Inputs LVCMOS, LVTTL, CML, PECL, synchronously enables or disables the outputs on the next LVDS, and HSTL falling edge of IN (rising edge of /N). TTL/CMOS inputs for select and reset Use the SY89874U version, which has a wider input 100k EP-compatible LVPECL outputs range, to DC-couple low offset differential signals. Parallel programming capability Datasheets and support documentation can be found on Programmable divider ratios of 1, 2, 4, 8, and 16 Micrels web site at: www.micrel.com. Low-voltage operation 2.5V or 3.3V Output disable function 40C to +85C temperature range Available in 16-pin (3mm x 3mm) QFN package Applications SONET/SDH line cards Transponders High-end multiprocessor sensors United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY89874AU (1) Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish SY89874AUMG QFN-16 Industrial 874U Pb-Free (2) SY89874AUMGTR QFN-16 Industrial 874U Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. Pin Configuration 16-Pin QFN Pin Description Pin Number Pin Name Pin Function Input. Internal 50 termination resistors to VT input. Flexible input accepts any input. See the Input 12, 9 IN, /IN Interface Applications section. Q0, /Q0 Differential Buffered LVPECL Outputs. Divided by 1, 2, 4, 8, or 16. See the Truth Table. Unused 1, 2, 3, 4 PECL outputs may be left floating with no impact on jitter performance. Q1, /Q1 Select Pins. See the Truth Table. LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic 16, 15, 5 S0, S1, S2 high if left unconnected (divided by 16 mode). Input threshold is V /2. CC 6 NC No Connect. LVTTL/CMOS Logic Levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected. Apply /RESET LOW to reset the divider (divided by 2, 4, 8, or 16 mode). Also acts as a synchronous disable/enable 8 function. The reset and disable function occurs on the next high-to-low clock input transition. Input /DISABLE threshold is V /2. CC Reference Voltage. Equal to V 1.4V (approximately). Used for AC-coupled applications only. CC 10 VREF-AC Decouple the VREF-AC pin with a 0.01F capacitor. See the Input Interface Applications section. Termination Center Tap. For CML or LVDS inputs, leave this floating. Otherwise, see Figures 3a to 3f 11 VT in the Input Interface Applications section. 7, 14 VCC Positive Power Supply. Bypass with .01F/0.01F low-ESR capacitor. 13 GND Ground. M9999-121812-A December 2012 2 hbwhelp micrel.com or (408) 955-1690