ZL30101 T1/E1 Stratum 3 System Synchronizer Data Sheet April 2010 Features Supports Telcordia GR-1244-CORE Stratum 3 Ordering Information Supports G.823 and G.824 for 2048 kbit/s and ZL30101QDG1 64 Pin TQFP* Trays, Bake & Drypack 1544 kbit/s interfaces *Pb Free Matte Tin Supports ANSI T1.403 and ETSI ETS 300 011 for -40C to +85C ISDN primary rate interfaces Simple hardware control interface External master clock source: clock oscillator or Accepts two input references and synchronizes to crystal any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs Applications Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz & Synchronization and timing control for multi-trunk 8.192 MHz or 32.768 MHz & 65.536 MHz DS1/E1 systems such as DSLAMs, gateways and PBXs Hitless reference switching between any combination of valid input reference frequencies Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) buses Provides 5 styles of 8 kHz framing pulses -8 Holdover frequency accuracy of 1 x 10 Lock, Holdover and Out of Range indication Selectable loop filter bandwidth of 1.8 Hz or 922 Hz Less than 0.6 ns jitter on all output clocks pp TIE CLR OSCi OSCo BW SEL LOCK OUT SEL Master Clock C2o Virtual C4/C65o REF0 TIE Reference MUX Corrector C8/C32o REF1 Circuit E1 DPLL C16o Synthesizer F4/F65o F8/F32o F16o REF FAIL0 TIE Reference Mode Corrector REF FAIL1 Monitor DS1 Control C1.5o Enable Synthesizer Feedback Frequency REF SEL Select MUX State Machine RST IEEE TRST 1149.1a MODE SEL1:0 HOLDOVER HMS TCK TDI TMS TDO Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2010, Zarlink Semiconductor Inc. All Rights Reserved.ZL30101 Data Sheet Description The ZL30101 Stratum 3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment. The ZL30101 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable. The ZL30101 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications. 2 Zarlink Semiconductor Inc.