Register Map: Section 4.2 TM ZL40255 SmartBuffer 3-Output Programmable Fanout Buffer with Multi-Format I/O and Dividers Data Sheet April 2018 Ordering Information Features ZL40255LDG1 32 Pin QFN Trays Four Input Clocks ZL40255LDF1 32 Pin QFN Tape and Reel One crystal/CMOS input Two differential/CMOS inputs Matte Tin One single-ended/CMOS input Package size: 5 x 5 mm Any input frequency up to 1035MHz (up to -40 C to +85 C 300MHz for CMOS) Clock selection by pin or register control General Features Up to 3 Differential Outputs (Up to 6 CMOS) Automatic self-configuration at power-up from Output frequencies are any integer divisor up to internal EEPROM up to four configurations, 32 2 of the input frequency (CMOS 250MHz max) pin-selectable Each output has independent dividers Crystal interface for frequency synthesis up to Low additive jitter <200fs RMS (12kHz-20MHz, 60MHz for input frequencies 100MHz) Four general-purpose I/O pins, each with many Outputs are CML or 2xCMOS, can interface to status and control options LVDS, LVPECL, HSTL, SSTL and HCSL 2 SPI or I C processor Interface In 2xCMOS mode, the P and N pins can be Tiny 5x5mm QFN package * different frequencies (e.g. 125MHz and 25MHz) Per-output supply pin with CMOS output Applications voltages from 1.5V to 3.3V Frequency synthesis up to 60MHz Precise output alignment circuitry and per- * Fanout up to 1035MHz output phase adjustment Format conversion, frequency division, and skew Per-output enable/disable and glitchless * adjustment in a wide variety of equipment types start/stop (stop high or low) Block Diagram Application Example 1: 156.25MHz differential 625MHz IC1P, IC1N HSDIV1 OC1P, OC1N DIV1 from other 125MHz differential ZL40255 VDDO1 IC2P, IC2N HSDIV2 timing IC OC2P, OC2N DIV2 2x 25MHz 1.8V CMOS IC3P/GPIO3 HSDIV3 VDDO2 OC3P, OC3N DIV3 XA crystal Application Example 2: VDDO3 driver XB 2x 100MHz differential (HCSL) Microprocessor Port 100MHz ZL40255 (SPI or I2C Serial) 2x 50MHz 2.5V CMOS and HW Control and Status Pins Application Example 3: 2x 50MHz 3.3V CMOS ZL40255 50MHz 2x 50MHz 1.8V CMOS 2x 25MHz 1.8V CMOS Figure 1 - Functional Block Diagram and Application Examples * Some features require a higher-frequency input clock and enabling the output dividers. 1 Microsemi Corporation Copyright 2018. Microsemi Corporation. All Rights Reserved. RSTN AC0/GPIO0 AC1/GPIO1 TEST/GPIO2 IC3P/GPIO3 IF0/CSN IF1/MISO SCL/SCLK SDA/MOSI ZL40255 Data Sheet Table of Contents 1. PIN DIAGRAM ............................................................................................................................... 4 2. PIN DESCRIPTIONS ..................................................................................................................... 5 3. FUNCTIONAL DESCRIPTION ...................................................................................................... 7 3.1 DEVICE IDENTIFICATION ................................................................................................................ 7 3.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ............................................................. 7 3.3 EXTERNAL CRYSTAL AND ON-CHIP DRIVER CIRCUIT ....................................................................... 8 3.4 INPUT SIGNAL FORMAT CONFIGURATION ........................................................................................ 8 3.5 INPUT SELECTION ......................................................................................................................... 9 3.6 OUTPUT CLOCK CONFIGURATION .................................................................................................. 9 3.6.1 Output Enable, Signal Format, Voltage and Interfacing ........................................................................ 9 3.6.2 Output Frequency Configuration ............................................................................................................ 9 3.6.3 Output Duty Cycle Adjustment ............................................................................................................. 10 3.6.4 Output Phase Adjustment and Phase Alignment ................................................................................. 10 3.6.5 Output Clock Start and Stop ................................................................................................................ 13 3.7 MICROPROCESSOR INTERFACE ................................................................................................... 14 3.7.1 SPI Slave ............................................................................................................................................. 14 2 3.7.2 I C Slave .............................................................................................................................................. 16 3.8 INTERRUPT LOGIC ...................................................................................................................... 18 3.9 RESET LOGIC ............................................................................................................................. 18 3.10 POWER-SUPPLY CONSIDERATIONS .......................................................................................... 19 3.11 AUTO-CONFIGURATION FROM EEPROM .................................................................................. 19 3.11.1 Factory-Default Device Configurations ................................................................................................ 19 3.11.2 Direct EEPROM Write Mode ................................................................................................................ 19 3.12 POWER SUPPLY DECOUPLING AND LAYOUT RECOMMENDATIONS ............................................... 19 4. REGISTER DESCRIPTIONS ....................................................................................................... 19 4.1 REGISTER TYPES ....................................................................................................................... 20 4.1.1 Status Bits ............................................................................................................................................ 20 4.1.2 Configuration Fields ............................................................................................................................. 20 4.1.3 Bank-Switched Registers ..................................................................................................................... 20 4.2 REGISTER MAP .......................................................................................................................... 20 4.3 REGISTER DEFINITIONS .............................................................................................................. 22 4.3.1 Global Configuration Registers ............................................................................................................ 22 4.3.2 Status Registers ................................................................................................................................... 28 4.3.3 Source Selection Configuration Registers ........................................................................................... 33 4.3.4 Output Clock Configuration Registers .................................................................................................. 34 4.3.5 Input Clock Configuration Registers .................................................................................................... 38 5. ELECTRICAL CHARACTERISTICS ........................................................................................... 39 6. PACKAGE AND THERMAL INFORMATION .............................................................................. 49 6.1 PACKAGE TOP MARK FORMAT ..................................................................................................... 49 6.2 THERMAL SPECIFICATIONS .......................................................................................................... 50 7. MECHANICAL DRAWING .......................................................................................................... 51 8. ACRONYMS AND ABBREVIATIONS ......................................................................................... 52 9. DATA SHEET REVISION HISTORY ........................................................................................... 52 2 Microsemi Corporation