Preliminary 216-Ball and 220-Ball, Dual-Channel Embedded LPDDR2 SDRAM Features Embedded LPDDR2 SDRAM EDB8164B4PR, EDB8164B4PK, EDB8164B4PT, EDBA164B2PR Options Marking Features Density/Page Size Ultra-low-voltage core and I/O power supplies 8Gb/2-CS dual die 81 Frequency range 16Gb/4-CS quad die A1 533 MHz (data rate: 1066 Mb/s/pin) Organization 4n prefetch DDR architecture x64 64 8 internal banks for concurrent operation V /V /V : 1.8V/1.2V/1.2V B DD1 DD2 DDQ Multiplexed, double data rate, command/address Revision inputs commands entered on each CK t/CK c Dual die 2 edge Quad die 4 Bidirectional/differential data strobe per byte of FBGA green package data (DQS t/DQS c) 12mm x 12mm x 0.8mm, 216-ball PR Programmable READ and WRITE latencies (RL/WL) PoP FBGA package, dual die Burst length: 4, 8, and 16 12mm x 12mm x 0.8mm, 216-ball PT Per-bank refresh for concurrent operation PoP FBGA package, dual die Auto temperature-compensated self refresh 12mm x 12mm x 1.0mm, 216-ball PR (ATCSR) by built-in temperature sensor PoP FBGA package, quad die Partial-array self refresh (PASR) 14mm x 14mm x 0.7mm, 220-ball PK Deep power-down mode (DPD) PoP FBGA package, dual die Selectable output drive strength (DS) Timing cycle time Clock-stop capability 1.875ns RL = 8 -1D Lead-free (RoHS-compliant) and halogen-free Special options packaging Non-Automotive blank Operating temperature range From 30C to +85C blank Table 1: Key Timing Parameters From 40C to +85C IT From 40C to +105C AT Speed Clock Rate Data Rate Grade (MHz) (Mb/s/pin) RL WL 1D 533 1066 8 4 Table 2: S4 Configuration Addressing Architecture 128 Meg x 64 256 Meg x 64 Die configuration 16 Meg x 32 x 8 banks x 2 channel 32 Meg x 32 x 8 banks x 2 channel Row addressing 16K A 13:0 16K A 13:0 Column addressing 1K A 9:0 1K A 9:0 Number of die 2 4 Die per rank 1 2 Ranks per channel 1 2 1. A channel is a complete LPDRAM interface, including command/address and data pins. Note: PDF: 09005aef85eb530a Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 216b 220b 2ch 2e0e embedded lpddr2.pdf Rev. E 5 /16 EN 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Microns production data sheet specifications.Preliminary 216-Ball and 220-Ball, Dual-Channel Embedded LPDDR2 SDRAM Features Figure 1: LPDDR2 Part Numbering E D B 81 64 B 4 PR -1D IT F - D Micron Technology Packing Media D = Dry Pack (Tray) R = Tape and Reel Type D = Packaged device Environment Code F = Lead-free (RoHS-compliant) and halogen-free Product Family B = Mobile LPDDR2 SDRAM Operating Temperature Density/Chip Select Blank = 30C to +85C IT = 40C to +85C 81 = 8Gb/2-CS AT = 40C to +105C A1 = 16Gb/4-CS (2-CS/channel) Organization Special options 64 = x64 Blank = Non-Automotive Power Supply Interface Speed B = V = 1.8V, V = V = 1.2V, 1D = 1066 Mb/s DD1 DD2 DDQ S4B device, HSUL Package PR = BGA for Pop PT = BGA for Pop PK = BGA for Pop Revision FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. Table 3: Package Codes and Descriptions Package Ball Chan- Die per Solder Ball Code Count Ranks nels Size (mm) Package Composition PR 216 1 2 12mm x 12mm x 0.80mm, 0.40 pitch DDP SAC302 PT 216 1 2 12mm x 12mm x 0.80mm, 0.40 pitch DDP SAC302 PR 216 2 2 12mm x 12mm x 1.00mm, 0.40 pitch QDP SAC302 PK 220 1 2 14mm x 14mm x 0.70mm, 0.50 pitch DDP SAC302 1. DDP = dual-die package, QDP = quad-die package Notes: 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). PDF: 09005aef85eb530a Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 216b 220b 2ch 2e0e embedded lpddr2.pdf Rev. E 5 /16 EN 2014 Micron Technology, Inc. All rights reserved.