MT46H64M32LFBQ-48 WT:C TR

152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Features Mobile LPDDR (only) 152-Ball Package-on-Package (PoP) TI-OMAP MT46HxxxMxxLxCG MT46HxxxMxxLxKZ Options Marking Features V /V = 1.701.95V V /V DD DDQ DD DDQ Bidirectional data strobe per byte of data (DQS) 1.8V/1.8V H Configuration Internal, pipelined double data rate (DDR) 128 Meg x 32 (16 Meg x 16 x 4 banks x 4) 128M32 architecture 2 data accesses per clock cycle 64 Meg x 32 (8 Meg x 32 x 4 banks x 2) 64M32 Differential clock inputs (CK and CK ) 32 Meg x 32 (8 Meg x 32 x 4 banks) 32M32 Commands entered on each positive CK edge 16 Meg x 32 (4 Meg x 32 x 4 banks) 16M32 DQS edge-aligned with data for READs center- Device version aligned with data for WRITEs Single die, standard addressing LF 4 internal banks for concurrent operation 2-die stack, standard addressing L2 Data masks (DM) for masking write dataone mask 4-die stack, standard addressing L4 per byte 1 Plastic green package Programmable burst lengths (BLs): 2, 4, 8, or 16 152-ball VFBGA (14 x 14 x 1.0mm) CG Concurrent auto precharge option is supported 152-ball VFBGA (14 x 14 x 1.2mm) KZ Auto refresh and self refresh modes Timing cycle time 1.8V LVCMOS-compatible inputs 5ns CL = 3 -5 On-chip temperature sensor to control self refresh 5.4ns CL = 3 -54 rate 6ns CL = 3 -6 Partial-array self refresh (PASR) Operating temperature range Deep power-down (DPD) Commercial (0C to +70C) None 2 STATUS REGISTER READ (SRR) supported Industrial (40C to +85C) IT Selectable output drive strength (DS) Clock stop capability Notes: 1. BL 16: contact factory for availability. 64ms refresh 2. Contact factory for remapped SRR output. Table 1: Configuration Addressing 1 Architecture 128 Meg x 32 64 Meg x 32 32 Meg x 32 16 Meg x 32 Configuration 16 Meg x 16 8 Meg x 32 8 Meg x 32 4 Meg x 32 x 4 banks x 4 die x 4 banks x 2 die x 4 banks x 4 banks Refresh count 8K 8K 8K 8K 16K (A 13:0 ) 8K (A 12:0 ) 8K (A 12:0 ) 8K (A 12:0 ) Row addressing Column addressing 1K (A 9:0 ) 1K (A 9:0 ) 1K (A 9:0 ) 512 (A 8:0 ) Notes: 1. Quad die stack. Each CS configured with two x16 die connected in parallel to make up a 32-bit- wide bus. PDF: 09005aef833913f1/Source: 09005aef833913d6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ddr mobile sdram only 152b omap pop.fm - Rev. E 06/09 EN 1 2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Part Numbering Information 152-Ball PoP Part Numbering Information 152-Ball PoP Micron 152-ball packaged LPDDR devices are available in several configurations. Figure 1: Marketing Part Number Example MT 46 H 32M32 LF CG -6 IT :A Micron Technology Design Revision :A = First generation Product Family :B = Second generation 46 = LPDDR-SDRAM Operating Temperature Operating Voltage Blank = Commercial (0C to +70C) H = 1.8V/1.8V IT = Industrial (40C to +85C) Configuration Cycle Time t 128 Meg x 32 -5 = 5ns CK CL = 3 t 64 Meg x 32 -54 = 5.4ns CK CL = 3 t 32 Meg x 32 -6 = 6ns CK CL = 3 16 Meg x 32 Package Code Device Version CG = 152-ball (14 x 14 x 1.0mm) VFBGA LF = Single die, standard addressing KZ = 152-ball (14 x 14 x 1.2mm) VFBGA L2 = 2-die stack, standard addressing L4 = Quad die, standard addressing PDF: 09005aef833913f1/Source: 09005aef833913d6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ddr mobile sdram only 152b omap pop.fm - Rev. E 06/09 EN 2 2008 Micron Technology, Inc. All rights reserved.