1Gb: x4, x8, x16 DDR SDRAM Features DDR SDRAM MT46V256M4 64 Meg x 4 x 4 Banks MT46V128M8 32 Meg x 8 x 4 Banks MT46V64M16 16 Meg x 16 x 4 Banks Features Options Marking VDD = 2.5V 0.2V, VDDQ = 2.5V 0.2V Configuration VDD = 2.6V 0.1V, VDDQ = 2.6V 0.1V (DDR400) 256 Meg x 4 (64 Meg x 4 x 4 banks) 256M4 Bidirectional data strobe (DQS) transmitted/ 128 Meg x 8 (32 Meg x 8 x 4 banks) 128M8 received with data, that is, source-synchronous data 64 Meg x 16 (16 Meg x 16 x 4 banks) 64M16 capture (x16 has two one per byte) Plastic package OCPL Internal, pipelined double-data-rate (DDR) 66-pin TSOP TG architecture two data accesses per clock cycle (400-mil width, 0.65mm pin pitch) Differential clock inputs (CK and CK ) 66-pin TSOP (Pb-free) P Commands entered on each positive CK edge (400-mil width, 0.65mm pin pitch) DQS edge-aligned with data for READs center- Timing cycle time aligned with data for WRITEs 1 5.0ns CL = 3 (DDR400B) -5B DLL to align DQ and DQS transitions with CK 2 6.0ns CL = 2.5 (DDR333B) -6T Four internal banks for concurrent operation 2 7.5ns CL = 2.5 (DDR266B) -75 Data mask (DM) for masking write data Temperature rating (x16 has two one per byte) Commercial (0 C to +70 C) None Programmable burst lengths (BL): 2, 4, or 8 Industrial (40C to +85C) IT Auto refresh and self refresh modes Revision :A Longer-lead TSOP for improved reliability (OCPL) Notes: 1. Not recommended for new designs. 2.5V I/O (SSTL 2 compatible) Concurrent auto precharge option is supported 2. See Table 3 on page 2 for module t t t RAS lockout supported ( RAP = RCD) compatibility. Table 1: Key Timing Parameters CL = CAS (READ) latency data-out window is MIN clock rate with 50 percent duty cycle at CL = 2.5 Clock Rate (MHz) Data-Out Access DQSDQ Speed Grade CL = 2 CL = 2.5 CL = 3 Window Window Skew -5B 133 167 200 1.6ns 0.70ns 0.40ns -6T 133 167 n/a 2.0ns 0.70ns 0.45ns -75 100 133 n/a 2.5ns 0.75ns 0.50ns PDF: 09005aef80a2f898/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb DDR x4x8x16 D1.fm - 1Gb DDR: Rev. J, Core DDR: Rev. E 7/11 EN 1 2003 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR SDRAM Features Table 2: Addressing Parameter 256 Meg x 4 128 Meg x 8 64 Meg x 16 Configuration 64 Meg x 4 x 4 banks 32 Meg x 8 x 4 banks 16 Meg x 16 x 4 banks Refresh count 8K 8K 8K Row address 16K (A0A13) 16K (A0A13) 16K (A0A13) Bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Column address 4K (A0A9, A11, A12) 2K (A0A9, A11) 1K (A0A9) Table 3: Speed Grade Compatibility Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2) Yes Yes Yes Yes Yes Yes -5B Yes Yes Yes Yes Yes -6T Yes Yes -75 -5B -6T -75 -75 -75 -75 Figure 1: 1Gb DDR SDRAM Part Numbers Example Part Number: MT46V64M16P-6T:A : - Sp. MT46V Configuration Package Speed Temp. Revision Op. Revision :A x4, x8, x16 Configuration 256 Meg x 4 256M4 Operating Temperature 128 Meg x 8 128M8 Commercial 64 Meg x 16 64M16 Industrial IT Package Special Options 400-mil TSOP TG Standard 400-mil TSOP (Pb-free) P Speed Grade t -5B CK = 5ns, CL = 3 t -6T CK = 6ns, CL = 2.5 t -75 CK = 7.5ns, CL = 2.5 PDF: 09005aef80a2f898/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 1Gb DDR x4x8x16 D1.fm - 1Gb DDR: Rev. J, Core DDR: Rev. E 7/11 EN 2 2003 Micron Technology, Inc. All rights reserved.