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AS4C2M32D1A-5BIN

AS4C2M32D1A-5BIN electronic component of Alliance Memory

Datasheet
DRAM DDR1, 64M, 2.5V 200MHz,2M x 32
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 6.1687 ea
Line Total: USD 6.17

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1

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Ships to you between Tue. 04 Jun to Thu. 06 Jun

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AS4C2M32D1A-5BIN
Alliance Memory

1 : USD 4.4969
10 : USD 4.1291
100 : USD 3.6782
189 : USD 3.6782
567 : USD 3.6426
1134 : USD 3.5595
1890 : USD 3.4884
5670 : USD 3.3934
11340 : USD 3.3697

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Additional Infomation About Product

AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Revision History AS4C2M32D1A - 144 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Dec 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential 1 of 63 Rev.1.0 Dec 2015AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Features Overview The 64Mb DDR SDRAM is a high-speed CMOS Fast clock rate: 200 MHz double data rate synchronous DRAM containing 64 Mbits. Differential Clock CK & CK It is internally configured as a quad 512K x 32 DRAM Bi-directional DQS with a synchronous interface (all signals are registered DLL enable/disable by EMRS on the positive edge of the clock signal, CK). Fully synchronous operation Data outputs occur at both rising edges of CK and . CK Read and write accesses to the SDRAM are burst Internal pipeline architecture oriented accesses start at a selected location and Four internal banks, 512K x 32-bit for each bank continue for a programmed number of locations in a Programmable Mode and Extended Mode registers programmed sequence. Accesses begin with the - CAS Latency: 2, 2.5, 3 registration of a BankActivate command which is then - Burst length: 2, 4, 8 followed by a Read or Write command. The device - Burst Type: Sequential & Interleaved provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to Individual byte write mask control provide a self-timed row precharge that is initiated at the DM Write Latency = 0 end of the burst sequence. The refresh functions, either Auto Refresh and Self Refresh Auto or Self Refresh are easy to use. In addition, 64Mb 4096 refresh cycles / 64ms DDR features programmable DLL option. By having a Precharge & active power down programmable mode register and extended mode register, Operating Temperature: the system can choose the most suitable modes to maximize its performance. These devices are well suited - Commercial (0 ~ 70 C) - Industrial (-40 ~ 85 C) for applications requiring high memory bandwidth result in a device particularly well suited to high performance main Power supplies: VDD & VDDQ = 2.5V 0.2V memory and graphics applications. Interface: SSTL 2 I/O Interface 144-ball 12 x 12 x 1.4mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Org Temperature Max Clock (MHz) Product part No Package AS4C2M32D1A-5BCN Commercial 0C to 70C 200 144-ball FBGA 2Mx 32 AS4C2M32D1A-5BIN Industrial -40C to 85C 200 144-ball FBGA 2Mx 32 Confidential 2 of 63 Rev.1.0 Dec 2015

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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