74AUP1T08GW-Q100H Nexperia

74AUP1T08-Q100 Low-power 2-input AND gate with voltage-level translator Rev. 1 15 July 2021 Product data sheet 1. General description The 74AUP1T08-Q100 provides the single 2-input AND function. This device ensures a very low static and dynamic power consumption across the entire V range from 2.3 V to 3.6 V. CC The 74AUP1T08-Q100 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire V range. CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.3 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 1.5 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1T08GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package SOT353-1 5 leads body width 1.25 mmNexperia 74AUP1T08-Q100 Low-power 2-input AND gate with voltage-level translator 4. Marking Table 2. Marking Type number Marking code 1 74AUP1T08GW-Q100 5J 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 B B 1 Y 4 & 4 Y 2 A 2 A aaa-027689 aaa-027690 aaa-027691 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1T08 1 5 B V CC 2 A GND 3 4 Y aaa-027693 Fig. 4. Pin configuration SOT353-1 (TSSOP5) 6.2. Pin description Table 3. Pin description Symbol Pin Description B 1 data input A 2 data input GND 3 ground (0 V) Y 4 data output V 5 supply voltage CC 74AUP1T08 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 1 15 July 2021 2 / 13