Product Information

74AUP2G38DC,125

74AUP2G38DC,125 electronic component of Nexperia

Datasheet
NAND Gate 2-Element 2-IN CMOS 8-Pin VSSOP
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.4761 ea
Line Total: USD 0.48

1455 - Global Stock
Ships to you between
Fri. 10 May to Tue. 14 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
1455 - Warehouse 1


Ships to you between Fri. 10 May to Tue. 14 May

MOQ : 1
Multiples : 1
1 : USD 0.4761
10 : USD 0.3806
100 : USD 0.2829
500 : USD 0.2438
1000 : USD 0.1944
3000 : USD 0.1484
9000 : USD 0.1484
24000 : USD 0.1449
45000 : USD 0.1438

Read More Specifications

     
Manufacturer
Product Category
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Technology
Logical Function
Mounting
Operating Temp Range
Output Type
Package Type
Pin Count
Quiescent Current
Number Of Elements
Operating Temperature Classification
Number Of Inputs
Number Of Outputs
Rad Hardened
Operating Supply Voltage Typ
Operating Supply Voltage Min
Operating Supply Voltage Max
Height
Length
Width
Brand
Logic Type
Cnhts
Hts Code
Mxhts
Product Type
Factory Pack Quantity :
Subcategory
Taric
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Additional Infomation About Product

74AUP2G38 Low-power dual 2-input NAND gate open drain Rev. 10 3 December 2020 Product data sheet 1. General description The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using I . The I circuitry OFF OFF disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AUP2G38 Low-power dual 2-input NAND gate open drain 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G38DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74AUP2G38GT -40 C to +125 C XSON8 plastic extremely thin small outline package SOT833-1 no leads 8 terminals body 1 1.95 0.5 mm 74AUP2G38GN -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 1.0 0.35 mm 74AUP2G38GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 1.0 0.35 mm 4. Marking Table 2. Marking codes Type number Marking code 1 74AUP2G38DC a38 74AUP2G38GT a38 74AUP2G38GN aB 74AUP2G38GS aB 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram & 1A Y 1Y 1B A 2A & 2Y 2B B GND 001aah753 001aah754 mnb131 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 74AUP2G38 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 10 3 December 2020 2 / 17

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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