74HC137D,652 Nexperia

74HC137 3-to-8 line decoder, demultiplexer with address latches inverting Rev. 5 4 August 2021 Product data sheet 1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to HIGH transition on LE stores the data that was present before the transition in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable inputs control the state of the outputs independently of the address inputs or latch operation. All outputs will be HIGH unless E1 is LOW and E2 is HIGH. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Combines 3-to-8 decoder with 3-bit latch Multiple input enable for easy expansion or independent controls Active LOW mutually exclusive outputs Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +80 C and from -40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC137D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HC137DB -40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74HC137PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mmNexperia 74HC137 3-to-8 line decoder, demultiplexer with address latches inverting 4. Functional diagram 4 LE Y0 15 Y1 14 Y2 13 A0 1 Y3 12 2 A1 INPUT 3 TO 8 Y4 11 LATCHES DECODER 3 A2 Y5 10 Y6 9 Y7 7 5 E1 6 E2 001aab881 Fig. 1. Functional diagram DX 4 15 C8 0 1 14 0 1 2 0 13 8D,G 2 7 3 12 3 2 11 4 10 5 5 9 & 6 4 7 6 7 LE 15 Y0 14 X/Y Y1 13 4 15 Y2 C8 0 1 A0 12 1 14 Y3 8D,1 1 2 INPUT 3 TO 8 A1 11 2 13 LATCHES DECODER Y4 8D,2 2 3 A2 10 3 12 Y5 8D,4 3 9 11 Y6 4 7 10 Y7 5 5 9 & 6 6 7 E1 7 5 001aab879 EN 6 E2 001aab880 Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74HC137 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 4 August 2021 2 / 16