74HC4351D,653

74HC4351 74HCT4351 8-channel analog multiplexer/demultiplexer with latch Rev. 4 4 August 2021 Product data sheet 1. General description The 74HC4351 74HCT4351 is a single-pole octal-throw analog switch (SP8T) suitable for use in analog or digital 8:1 multiplexer/demultiplexer applications. The switch features three digital select inputs (S0 to S2), eight independent inputs/outputs (Yn), a common input/output (Z) and two digital enable inputs (E1 and E2). With E1 LOW and E2 HIGH, one of the eight switches is selected (low impedance ON-state) by S0 to S2. The data at the select inputs may be latched by using the latch enable input (LE). When LE is HIGH the latch is transparent. When E1 is HIGH or E2 is LOW all 8 analog switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide analog input voltage range from -5 V to +5 V Complies with JEDEC standard no. 7A Low ON resistance: 80 (typical) at V - V = 4.5 V CC EE 70 (typical) at V - V = 6.0 V CC EE 60 (typical) at V - V = 9.0 V CC EE Logic level translation: to enable 5 V logic to communicate with 5 V analog signals Typical break before make built-in Address latches provided ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4351D -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74HCT4351D 74HC4351DB -40 C to +125 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74HC4351PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mmNexperia 74HC4351 74HCT4351 8-channel analog multiplexer/demultiplexer with latch 5. Functional diagram 20 V CC Y0 17 S0 15 Y1 18 S1 13 S2 12 Y2 19 LE 11 Y3 16 LOGIC LEVEL 1-OF-8 Y4 1 CONVERSION DECODER AND LATCHES Y5 6 Y6 2 E1 7 E2 8 Y7 5 Z 4 GND V EE aaa-028752 10 9 Fig. 1. Functional diagram 15 0 13 0 2D, 1 X 7 12 2 7 & G1 8 15 17 S0 Y0 9 C2 13 18 S1 Y1 12 19 S2 Y2 MUX/DMUX 17 16 0 Y3 18 1 11 1 19 LE Y4 2 6 16 Y5 3 4 1 7 2 4 E1 Y6 6 5 8 5 E2 Y7 2 6 Z 5 7 4 aaa-028753 aaa-028754 Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74HC HCT4351 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 4 August 2021 2 / 23