74HC86DB,112 Nexperia

74HC86 74HCT86 Quad 2-input EXCLUSIVE-OR gate Rev. 6 13 September 2021 Product data sheet 1. General description The 74HC86 74HCT86 is a quad 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC86: CMOS level For 74HCT86: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC86D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT86D 74HC86PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT86PWNexperia 74HC86 74HCT86 Quad 2-input EXCLUSIVE-OR gate 4. Functional diagram 1 1A 1Y 3 2 1B 4 2A 2Y 6 5 2B 9 3A 3Y 8 10 3B 12 4A 4Y 11 13 4B mna787 Fig. 1. Logic symbol 1 =1 3 2 4 =1 6 5 9 =1 8 10 A 12 Y =1 11 13 B mna788 mna786 Fig. 2. Logic diagram (one gate) Fig. 3. IEC logic symbol 5. Pinning information 5.1. Pinning 74HC86 74HCT86 1A 1 14 V CC 74HC86 74HCT86 1B 2 13 4B 1A 1 14 V 1Y 3 12 4A CC 1B 2 13 4B 2A 4 11 4Y 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y GND 7 8 3Y 001aad103 aaa-033304 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 74HC HCT86 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 13 September 2021 2 / 12