Product Information

74HCT109PW

74HCT109PW electronic component of Nexperia

Datasheet
Flip Flops DUAL J-K POS EDGE

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

5: USD 0.8348 ea
Line Total: USD 4.17

0 - Global Stock
MOQ: 5  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - WHS 1


Ships to you between Wed. 15 May to Tue. 21 May

MOQ : 5
Multiples : 1

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74HCT109PW
Nexperia

5 : USD 0.9015
100 : USD 0.6871
250 : USD 0.6388
500 : USD 0.5438
1000 : USD 0.4182
2400 : USD 0.4

     
Manufacturer
Product Category
Package / Case
Packaging
Brand
Logic Family / Base Number
Flip-Flop Type
Propagation Delay
Frequency
Output Current
Logic Case Style
No. Of Pins
Trigger Type
Ic Output Type
Supply Voltage Min
Supply Voltage Max
Logic Ic Family
Logic Ic Base Number
Operating Temperature Min
Operating Temperature Max
Rohs Phthalates Compliant
Msl
Svhc
Logic Function Number
Logic Ic Function
Operating Temperature Range
Supply Voltage Range
Termination Type
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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT109 Dual JK flip-flop with set and reset positive-edge trigger 1997 Nov 25 Product specication Supersedes data of December 1990 File under Integrated Circuits, IC06Philips Semiconductors Product specication Dual JK ip-op with set and reset 74HC/HCT109 positive-edge trigger FEATURES (S ) and reset (R ) inputs also complementary Q and Q D D outputs. J, K inputs for easy D-type flip-flop The set and reset are asynchronous active LOW inputs Toggle flip-flop or do nothing mode and operate independently of the clock input. Output capability: standard The J and K inputs control the state changes of the I category: flip-flops CC flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to GENERAL DESCRIPTION the LOW-to-HIGH clock transition for predictable The 74HC/HCT109 are high-speed Si-gate CMOS devices operation. and are pin compatible with low power Schottky TTL The JK design allows operation as a D-type flip-flop by (LSTTL). They are specified in compliance with JEDEC tying the J and K inputs together. standard no. 7A. Schmitt-trigger action in the clock input makes the circuit The 74HC/HCT109 are dual positive-edge triggered, JK highly tolerant to slower clock rise and fall times. flip-flops with individual J, K inputs, clock (CP) inputs, set QUICK REFERENCE DATA GND = 0 V T = 25 C t = t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay PHL PLH nCP to nQ, nQ1517ns C = 15 pF L nS to nQ, nQ1214ns D V = 5 V CC nR to nQ, nQ1215ns D f maximum clock frequency 75 61 MHz max C input capacitance 3.5 3.5 pF I C power dissipation 20 22 pF PD notes 1 and 2 capacitance per ip-op Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P = C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V. I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. 1997 Nov 25 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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