74LV02BQ Nexperia

74LV02 Quad 2-input NOR gate Rev. 04 20 December 2007 Product data sheet 1. General description The 74LV02 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC02 and 74HCT02. The 74LV02 provides a quad 2-input NOR function. 2. Features Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV02D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV02PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LV02BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package no leads 14 terminals body 2.5 3 0.85 mm74LV02 NXP Semiconductors Quad 2-input NOR gate 4. Functional diagram 2 1A 1Y 1 3 1B 2 5 1 2A 1 2Y 4 3 A 6 2B 5 8 Y 3A 1 4 3Y 10 6 9 3B B mna215 11 8 4A 4Y 13 1 10 12 4B 9 11 mna216 1 13 12 001aah084 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate 5. Pinning information 5.1 Pinning 74LV02 terminal 1 index area 2 13 1A 4Y 1Y 1 14 V 1B 3 12 4B CC 1A 2 13 4Y 2Y 4 11 4A 1B 3 12 4B (1) 2A 5 10 3Y V CC 2Y 4 02 11 4A 2B 6 9 3B 2A 5 10 3Y 2B 6 9 3B 001aah093 GND 7 8 3A 001aac919 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin conguration SO14 and TSSOP14 Fig 5. Pin conguration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1Y 1 data output 1A 2 data input 1B 3 data input 74LV02 4 NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 20 December 2007 2 of 12 7 1 GND 1Y 3A 8 14 V CC