74LVCH162373ADGG:1

74LVC162373A 74LVCH162373A 16-bit D-type transparent latch 30 series termination resistors 5 V tolerant inputs/outputs 3-state Rev. 6 16 September 2021 Product data sheet 1. General description The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with 30 termination resistors and 3-state outputs. The 74LVCH162373A has separate D-type inputs with bus hold for each latch. Both devices can be used as two 8-bit transparent latches or a single 16- bit transparent latch. Both devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. These devices are fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the devices when they are powered down. 2. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pinout architecture Multiple low inductance supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH162373A only) I circuitry provides partial Power-down mode operation OFF Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC162373ADGG -40 C to +125 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mm 74LVCH162373ADGGNexperia 74LVC162373A 74LVCH162373A 16-bit D-type transparent latch 30 series termination resistors 5 V tolerant inputs/outputs 3-state 4. Functional diagram 1 1EN 1 24 1OE 48 1LE C3 24 2OE 2EN 1OE 2OE 25 47 1D0 1Q0 2 C4 2LE 46 1D1 1Q1 3 2 47 1D0 1 1Q0 3D 44 1D2 1Q2 5 46 3 1D1 1Q1 43 1D3 1Q3 6 44 5 1D2 1Q2 1D4 1Q4 8 41 43 6 1D3 1Q3 40 1D5 1Q5 9 8 41 1D4 1Q4 38 1D6 1Q6 11 9 40 1D5 1Q5 37 1D7 1Q7 12 38 11 1D6 1Q6 36 2D0 2Q0 13 37 12 1D7 1Q7 14 35 2D1 2Q1 36 13 2D0 4D 2 2Q0 33 2D2 2Q2 16 35 14 2D1 2Q1 32 2D3 2Q3 17 16 33 2D2 2Q2 30 2D4 2Q4 19 17 32 2D3 2Q3 29 2D5 2Q5 20 30 19 2D4 2Q4 22 27 2D6 2Q6 29 20 2D5 2Q5 26 2D7 2Q7 23 27 22 2D6 2Q6 1LE 2LE 26 23 2D7 2Q7 mgu768 48 25 mgu770 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 1D0 D Q 1Q0 2D0 D Q 2Q0 LATCH LATCH 1 9 LE LE LE LE 1LE 2LE 1OE 2OE to 7 other channels to 7 other channels mgu769 Fig. 3. Logic diagram V CC input to internal circuit mna428 Fig. 4. Bus hold circuit 74LVC LVCH162373A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 16 September 2021 2 / 14