74LVT2245DB,118

74LVT2245 74LVTH2245 3.3 V octal transceiver with 30 termination resistors 3-state Rev. 7 17 August 2021 Product data sheet 1. General description The 74LVT2245 74LVTH2245 is an 8-bit transceiver with 30 termination resistors and 3-state outputs. The device features an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs 2. Features and benefits 30 output termination resistors Octal bidirectional bus interface 3-state buffers Wide supply voltage range from 2.7 to 3.6 V BiCMOS high speed and output drive Output capability: +12 mA and -12 mA TTL input and output switching levels Overvoltage tolerant inputs to 5.5 V Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Direct interface with TTL levels Power-up 3-state No bus current loading when output is tied to 5 V bus I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 500 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) ESD protection: MIL STD 883 method 3015: exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT2245D -40 C to +85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVTH2245D 74LVT2245PW -40 C to +85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVTH2245PWNexperia 74LVT2245 74LVTH2245 3.3 V octal transceiver with 30 termination resistors 3-state 4. Functional diagram 1 DIR 19 OE 2 A0 18 B0 19 3 G3 A1 17 3 EN1 (BA) B1 1 V V CC CC 4 3 EN2 (AB) A2 16 B2 5 A3 2 18 1 15 B3 2 6 A4 3 17 25 14 B4 4 16 7 A5 5 15 13 B5 25 14 6 8 A6 7 13 12 B6 8 12 9 A7 11 9 11 B7 mna817 mna818 mna819 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Schematic of one output 5. Pinning information 5.1. Pinning 74LVT2245 74LVT2245 74LVTH2245 74LVTH2245 1 20 DIR V DIR 1 20 V CC CC 2 19 A0 OE A0 2 19 OE 3 18 3 18 A1 B0 A1 B0 4 17 A2 B1 A2 4 17 B1 5 16 A3 B2 A3 5 16 B2 6 15 6 15 A4 B3 A4 B3 7 14 A5 B4 A5 7 14 B4 8 13 A6 B5 A6 8 13 B5 9 12 9 12 A7 B6 A7 B6 10 11 GND B7 GND 10 11 B7 aaa-026622 001aae465 Fig. 4. Pin configuration SOT163-1 (SO20) Fig. 5. Pin configuration SOT360-1 (TSSOP20) 74LVT LVTH2245 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 7 17 August 2021 2 / 12