74LVT244BPW,112 Nexperia

74LVT244B 74LVTH244B 3.3 V octal buffer/line driver 3-state Rev. 6 12 August 2021 Product data sheet 1. General description The 74LVT244B 74LVTH244B is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs 2. Features and benefits Octal bus interface 3-state buffers Speed upgrade of 74LVT244A Wide supply voltage range from 2.7 to 3.6 V BiCMOS high speed and output drive Output capability: +64 mA and -32 mA Direct interface with TTL levels Overvoltage tolerant inputs to 5.5 V Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs No bus current loading when output is tied to 5 V bus Power-up 3-state Live insertion and extraction permitted I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 500 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V MM EIA/JESD22-A115-A 200 V Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT244BD -40 C to +85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVTH244BD 74LVT244BPW -40 C to +85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVTH244BPWNexperia 74LVT244B 74LVTH244B 3.3 V octal buffer/line driver 3-state 4. Functional diagram 1A0 1Y0 2 18 1A1 1Y1 4 16 1A2 1Y2 6 14 1Y3 1A3 8 12 1 EN 1OE 1 18 2 16 4 2Y0 2A0 11 9 14 6 8 12 2A1 2Y1 13 7 19 EN 2A2 2Y2 15 5 11 9 2A3 2Y3 17 3 13 7 15 5 2OE 19 17 3 mna825 mna826 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 5. Pinning information 5.1. Pinning 74LVT244B 74LVT244B 74LVTH244B 74LVTH244B 1OE 1 20 V 1OE 1 20 V CC CC 1A0 2 19 2OE 2 19 1A0 2OE 2Y3 3 18 1Y0 2Y3 3 18 1Y0 1A1 4 17 2A3 1A1 4 17 2A3 2Y2 5 16 1Y1 5 16 2Y2 1Y1 1A2 6 15 2A2 1A2 6 15 2A2 2Y1 7 14 1Y2 2Y1 7 14 1Y2 1A3 8 13 2A1 8 13 1A3 2A1 2Y0 9 12 1Y3 2Y0 9 12 1Y3 GND 10 11 2A0 GND 10 11 2A0 aaa-033189 001aae463 Fig. 3. Pin configuration SOT163-1 (SO20) Fig. 4. Pin configuration SOT360-1 (TSSOP20) 74LVT LVTH244B All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 12 August 2021 2 / 12