HEF4555BP

HEF4555B 1-of-4 decoder/demultiplexer Rev. 5 18 November 2011 Product data sheet 1. General description The HEF4555B contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (nA0 and nA1, an active LOW enable input (nE) and four mutually exclusive outputs which are active HIGH (nY0 to nY3). When used as a decoder, nE when HIGH, forces nY0 to nY3 LOW. When used as a demultiplexer, the appropriate output is selected by the information on nA0 and nA1 with nE as data input. All unselected outputs are LOW. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications Code conversion Address decoding Demultiplexing: when using the enable input as data input 4. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF4555BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4555BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1HEF4555B NXP Semiconductors 1-of-4 decoder/demultiplexer 5. Functional diagram 1Y0 4 nY0 2 1A0 1Y1 5 nA0 DECODER 1Y2 6 3 1A1 1Y3 7 nY1 11E 2Y0 12 nA1 14 2A0 nY2 2Y1 11 DECODER 2Y2 10 13 2A1 2Y3 9 nE nY3 15 2E 001aae753 001aae751 Fig 1. Functional diagram Fig 2. Logic diagram for one decoder/multiplexer 6. Pinning information 6.1 Pinning HEF4555B 1E 1 16 V DD 1A0 2 15 2E 1A1 3 14 2A0 1Y0 4 13 2A1 5 12 1Y1 2Y0 1Y2 6 11 2Y1 10 1Y3 7 2Y2 V 8 9 2Y3 SS 001aae752 Fig 3. Pin configuration HEF4555B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 18 November 2011 2 of 13