NTE3093 Optoisolator NPN Split Darlington Output Description: The NTE3093 coupler uses a light emitting diode (LED) and an integrated high gain photon detector to provide 3000V DC electrical insulation, 500V/ s common mode transient immunity and extremely high current transfer ratio between inut and output. Separate pins for the photodiode and output stage result in TTL compatible saturation voltages and high speed operation. Where desired, the V and CC V terminals may be tied together to achieve conventional photodarlington operation. A base access O terminal allows a gain bandwidth adjustment to be made. Features: High Current Transfer Ratio Low Input Current Requirement TTL Compatible Output 3000V DC Withstand Test Voltage High Common Mode Rejection Base Access Allows Gain Bandwidth Adjustment High Output Current DC to 1Mbit/s Operation Absolute Maximum Ratings: (T = +25C unless otherwise specified) A Input Diode Reverse Voltage, V . 5V R Peak Current (50% Duty Cycle,1ms Pulse Width), I 40mA F Peak Transient Current ( 1 s Pulse Width, 300pps), I . 20mA F Power Dissipation, P 35mW D Derate Linearly Above 50C . 0.7mW/C Output Transistor Current (Pin6), I . 60mA O Derate Linearly Above 25C 0.7mA/C EmitterBase Reverse Voltage (Pin57) 0.5V Supply Voltage (Pin85), V . 0.5 to 18V CC Output Voltage (Pin65), V 0.5 to 18V O Power Dissipation, P 35mW D Derate Linearly Above 50C . 0.7mW/C Total Device Operating Temperature Range, T . 0 to +70C opr Storage Temperature Range, T 55 to +125C stg Lead Temperature (During Soldering, 1.6mm below seating plane, 10sec Max), T +260C L Note 1. The small junction sizes inherent to the design of this bipolar component increases the components susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to pre- vent damage and/or degredation which may be induced by ESD.Electrical Characteristics: (T = 0 to +70C, Note 2 unless otherwise specified) A Parameter Symbol Test Conditions Min Typ Max Unit Current Transfer Ratio CTR I = 0.5mA, V = 0.4V, V = 4.5V, Note 3, Note 4 400 800 % F O CC I = 1.6mA, V = 0.4V, V = 4.5V, Note 3, Note 4 500 900 % F O CC Logic Low Output Voltage V I = 1.6mA, I = 6.4mA, V = 4.5V, Note 4 0.1 0.4 V OL F O CC I = 5mA, I = 15mA, V = 4.5V, Note 4 0.1 0.4 V F O CC I = 12mA, I = 24mA, V = 4.5V, Note 4 0.2 0.4 V F O CC Logic High Output Current I I = 0, V = V = 18V, Note 4 0.05 100 A OH F O CC Logic Low Supply Current I I = 1.6mA, V = Open, V = 5V, Note 4 0.2 mA CCL F O CC Logic High Supply Current I I = 0mA, V = Open, V = 5V, Note 4 10 nA CCH F O CC Input Forward Voltage V I = 1.6mA, T = +25C 1.4 1.7 V F F A Input Reverse Breakdown V I = 10 A, T = +25C 5 V (BR)R F A Voltage Temperature Coefficient V I = 1.6mA 1.8 mV/C F F of Forward Voltage T A Input Capacitance C f = 1MHz, V = 0 60 pF IN F InputOutput Insulation I 45% Relative Humidity, T = +25C, t = 5s, 1.0 A IO A Leakage Currnt V = 3KVdc, Note 5 IO 11 Resistance R V = 500Vdc, Note 5 10 IO IO Capacitance C f = 1MHz, Note 5 0.6 pF IO Note 2. All typicals at T = +25C, V = 5V unless otherwise specified. A CC Note 3. DC Current Transfer Ratio is defined as the ratio of output collector current (I ) to the forward O LED input current (I ) times 100%. F Note 4. Pin7 Open. Note 5. Device considered a twoterminal device (Pins 1, 2, 3 and 4 shorted together and Pins 5, 6, 7 and 8 shorted together). Switching Characteristics: (T = +25C unless otherwise specified) A Parameter Symbol Test Conditions Min Typ Max Unit Propagation Delay Time t I = 0.5mA, R = 4.7k , Note 3, Note 6 5 25 s PHL F L I = 12mA, R = 270 , Note 3, Note 6 0.2 1.0 s F L t I = 0.5mA, R = 4.7k , Note 3, Note 6 5 60 s PLH F L I = 12mA, R = 270 , Note 3, Note 6 1 7 s F L Common Mode Transient Immunity CM I = 0, R = 2.2k , R = 0, 500 V/ s H F L CC V = 10V , Note 7, Note 8 CM PP CM I = 1.6mA, R = 2.2k , R = 0, 500 V/ s L F L CC V = 10V , Note 7, Note 8 CM PP Note 3. DC Current Transfer Ratio is defined as the ratio of output collector current (I ) to the forward O LED input current (I ) times 100%. F Note 6. Use of a resistor between Pin5 and Pin7 will decrease gain abd delay time. Note 7. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dv cm/dt on the leading edge of the common mode pulse (V ) to assure that the output will CM remain in a Logic High state (i.e. V 2.0V). Common mode transient immunity in Logic Low O level is the maximum tolerable (negative) dc cm/dt on the trailing edge of the common mode pulse signal (V ) to assure that the output will remain in a Logic Low state (i.e. V 0.8V). CM O Note 8. In applications where dV/dt may exceed 50,000V/ s (such as static discharge) a series re- sistor (R ) should be included to protect the detector IC from destructively high surge cur- CC rents. The recommended value is: 1V R = k CC 0.15 I (mA) F