74HC4520D

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4520 Dual 4-bit synchronous binary counter December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Dual 4-bit synchronous binary counter 74HC/HCT4520 FEATURES from all four bit positions (nQ to nQ ) and an active HIGH 0 3 overriding asynchronous master reset input (nMR). Output capability: standard The counter advances on either the LOW-to-HIGH I category: MSI CC transition of nCP if nCP is HIGH or the HIGH-to-LOW 0 1 transition of nCP if nCP is LOW. Either nCP or nCP 1 0 0 1 GENERAL DESCRIPTION may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH The 74HC/HCT4520 are high-speed Si-gate CMOS on nMR resets the counter (nQ to nQ = LOW) 0 3 devices and are pin compatible with the 4520 of the independent of nCP and nCP . 0 1 4000B series. They are specified in compliance with JEDEC standard no. 7A. APPLICATIONS The 74HC/HCT4520 are dual 4-bit internally synchronous binary counters with an active HIGH clock input (nCP ) 0 Multistage synchronous counting and an active LOW clock input (nCP ), buffered outputs 1 Multistage asynchronous counting Frequency dividers QUICK REFERENCE DATA GND = 0 V T =25C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay nCP , nCP to nQ C = 15 pF V = 5 V 2424ns PHL PLH 0 1 n L CC t propagation delay nMR to nQ 13 13 ns PHL n f maximum clock frequency 68 64 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per counter notes 1 and 2 29 24 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2