HEF4027B Dual JK flip-flop Rev. 9 18 November 2011 Product data sheet 1. General description The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications Registers Counters Control circuits 4. Ordering information Table 1. Ordering information T from 40 C to +85 C. amb Type number Package Name Description Version HEF4027BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4027BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1HEF4027B NXP Semiconductors Dual JK flip-flop 5. Functional diagram FF 1 9 1SD 10 1J 1Q 15 13 1CP 1Q 14 1K 11 1CD 12 FF 2 7 2SD 6 2J 2Q 1 3 2CP 2Q 2 2K 5 2CD 4 001aae593 Fig 1. Functional diagram CP Q C C C C C C J C C Q K C C CD SD 001aae595 Fig 2. Logic diagram of one flip-flop HEF4027B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 18 November 2011 2 of 14